GS1540-CQR Gennum Corporation, GS1540-CQR Datasheet - Page 14

• Manufacturer Part Number: GS1540-CQR
• Description: Hd-linx (tm) HDTV Serial Digital Non-equalizing Receiver
• Manufacturer: Gennum Corporation

JITTER DEMODULATION (DM)
The differential jitter demodulation (DM) signal is available
at the DM and DM pins. This signal is the phase correction
signal of the PLL loop, which is amplified and buffered. If
the input jitter is modulated, the PLL tracks the jitter if it is
within loop bandwidth. To track the input jitter, the VCO has
to be adjusted by the phase detector via the charge pump.
Thus, the signal which controls the VCO contains the
information of the input jitter modulation. The jitter
demodulation signal is only valid if the input jitter is less
than 0.5UIp-p. The DM/DM signals have 10kΩ output
impedance, which could be low pass filtered with
appropriate capacitors to eliminate high frequency noise.
DFT_V
signals.
The DM signals can be used as diagnostic tools. Assume
there is an HDTV SDI source, which contains excessive
noise during the horizontal blanking because of the
transient current flowing in the power supply. In order to
discover the source of the noise, one could probe around
the source board with a low frequency oscilloscope
(Bandwidth < 20MHz) that is triggered with an appropriately
filtered DM/DM signal. The true cause of the modulation will
be synchronous and will appear as a stationary signal with
respect to the DM/DM signal.
Figure 20 shows an example of such a situation. An HDTV
SDI signal is modulated with a modulation signal causing
about 0.2UI jitter in Figure 20 (Channel 1). The GS1540
receives this signal and locks to it. Figure 20 (Channel 2)
shows the DM signal. Notice the wave shape of the DM
signal, which is synchronous to the modulating signal. The
DM/DM signal could also be used to compare the output
jitter of the HDTV signal source.
GENNUM CORPORATION
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should be connected to GND to activate DM/DM
Fig. 20 Jitter Demodulation Signal
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LOCK LOGIC
Logic is used to produce the PLL_LOCK signal which is
based on the LFS signal and phase lock signal. When there
is not any data input, the integrator will charge and
eventually saturate at either end. By sensing the saturation
of the integrator, it is determined that no data is present. If
either data is not present or phase lock is low, the lock
signal is made low. Logic signals are used to acquire the
frequency by sweeping the integrator. Injecting a current
into the summing node of the integrator achieves the
sweep. The sweep is disabled once phase lock is asserted.
The direction of the sweep is also changed once LFS
saturates at either end.
BYPASS
The BYPASS block bypasses the reclocked/mute path of
the data whenever a logic low input is applied to the
BYPASS input. In the bypass mode, the mute does not have
any effect on the outputs. Also, the internal PLL still locks to
a valid HDTV signal and shows PLL_LOCK.
SERIAL OUTPUT STAGE
The serial output (DDO, DDO) signals have a nominal
voltage of 400mVpp differential, or 200mVpp single ended
when terminated with 50Ω.
DDO_EN
The DDO_EN enables or disables the serial output driver. To
disable the driver, tie DDO_EN to V
tie DDO_EN to V
reduced by approximately 10mA.
SERIAL TO PARALLEL CONVERTER
The high-speed serial to parallel converter accepts
differential clock and data signals from the reclocker core.
The S/P core converts this serial output into a 20-bit wide
data stream (D[19:0]). Note that this data stream is not word
aligned or descrambled. It also provides a parallel clock,
which is 1/20th the serial clock rate (PCLK_OUT). The
outputs of the S/P block are TTL compatible. When the PLL
loses lock, the parallel clock continues to freewheel. The
parallel clock and data outputs were designed for seamless
interfaces to the GS1500 and GS1510 deformatters.
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. When disabled, the supply current is
CC
. To enable the driver,
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