GS1540-CQR Gennum Corporation, GS1540-CQR Datasheet - Page 8

• Manufacturer Part Number: GS1540-CQR
• Description: Hd-linx (tm) HDTV Serial Digital Non-equalizing Receiver
• Manufacturer: Gennum Corporation

PIN DESCRIPTIONS (Continued)
PIN DESCRIPTIONS (Continued)
PIN DESCRIPTIONS (Continued)
PIN DESCRIPTIONS (Continued)
GENNUM CORPORATION
72
73
74
75
76
79, 80
81, 85
86
89
91
93, 96
98
105
106
108, 109
110
112
113
NUMBER
PLCAP, PLCAP
PDSUB_V
PLL_LOCK
SYMBOL
LBCONT
LFS, LFS
DDI, DDI
LFA_V
LFA_V
DFT_V
BYPASS
DM, DM
DDI_V
PD_V
PD_V
VCO
VCO
LFA
IJI
CC
EE
CC
EE
EE
TT
EE
Differential
ECL/PECL
LEVEL
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Power
Power
Power
Power
Power
Power
TTL
TTL
Output
Output
Output
Output
TYPE
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Positive Supply . Loop filter most positive power supply connection.
Control Signal Output. Control voltage for GO1515 VCO.
Control Signal Input . Used to provide electronic control of Loop
Bandwidth.
Negative Supply . Loop filter most negative power supply connection.
Most negative power supply connection - enables the jitter
demodulator functionality. This pin should be connected to ground. If
left floating, the DM function is disabled resulting in a current saving of
340µA.
Test Signal . Used for manufacturing test only.
These pins must be floating for normal operation.
Loop Filter Connections .
Status Signal Output . Approximates the amount of excessive jitter on
the incoming DDI and DDI input.
Control Signal Input . Input pin is AC coupled to ground using a 50 Ω
transmission line.
Control Signal Input. Voltage controlled oscillator input. This pin is
connected to the output pin of the GO1515 VCO.
This pin must be connected to the GO1515 VCO output pin via a 50 Ω
transmission line.
Control Signal Input . Phase lock detect time constant capacitor.
Status Indicator Signal . This signal is a combination (logical AND) of
the carrier detect and phase lock signals.
When input is present and PLL is locked, the PLL_LOCK goes high
and the outputs are valid. When the PLL_LOCK output is low the data
output is muted (latched at the last state).
PLL_LOCK is independent of the BYPASS signal.
Control Signal Input . Selectable input that controls whether the input
signal is reclocked or passed through the chip.
When BYPASS is high; the input signal is reclocked.
When BYPASS is low; the input signal is passed through the chip and
not reclocked. Muting does not effect bypassed signal.
Bias Input. Selectable input for interfacing standard ECL outputs
requiring 50 Ω pull down to V
See Typical Application Circuit for recommended circuit application.
Digital Data Input Signals. Digital input signals from a GS1504
Equalizer or HD crosspoint switch.
Because of on chip 50 Ω termination resistors, a PCB trace
characteristic impedance of 50 Ω is recommended.
Positive Supply . Phase detector most positive power supply
connection.
Substrate Connection . Connect to phase detector’s most negative
power supply.
Negative Supply. Phase detector most negative power supply
connection.
8
DESCRIPTION
TT
power supply for a seamless interface.
522 - 27 - 02