IDT82P2282 Integrated Device Technology, Inc., IDT82P2282 Datasheet - Page 201

• Manufacturer Part Number: IDT82P2282
• Description: 2 Channel T1/J1/E1 Transceiver
• Manufacturer: Integrated Device Technology, Inc.

IDT82P2282
T1/J1 THDLC1 Control (0A7H, 1A7H)
T1/J1 THDLC2 Control (0A8H, 1A8H)
T1/J1 THDLC3 Control (0A9H, 1A9H)
AUTOFISU:
FISU packet is transmitted with the BSN and FSN the same with the last transmitted packet.
EOM:
XREP:
flag, FCS and closing flag. This bit determines if this cyclic transmission can be implemented.
ABORT:
THDLCM:
Programming Information
Bit Name
Bit Name
Bit Name
Default
Default
Default
Bit No.
Bit No.
Bit No.
Type
Type
Type
The function of the above three sets of registers are the same. However, they correspond to different THDLC.
This bit is valid in SS7 mode when there is no data in the FIFO to be transmitted.
= 0: Normal operation.
= 1: The 7E (Hex) flags is transmitted N times (the ‘N’ is determined by the FL[1:0] bits (b5~4, T1/J1-0AAH,... / 0ABH,... / 0ACH,...)), then the
A transition from ‘0’ to ‘1’ on this bit indicates an entire HDLC/SS7 packet is stored in the FIFO and starts the packet transmission.
In SS7 mode, when the FIFO is empty, if less than 16 bytes are written into the FIFO, these bytes can be transmitted repeatedly with the opening
= 0: Disable the cyclic transmission.
= 1: Enable the cyclic transmission.
= 0: Disable the manual abort sequence insertion.
= 1: The abort sequence (‘01111111’) is manually inserted to the current HDLC/SS7 packet.
This bit is self-cleared after the abortion.
= 0: HDLC mode is selected.
= 1: SS7 mode is selected.
7
7
7
Reserved
Reserved
Reserved
6
6
6
AUTOFISU
AUTOFISU
AUTOFISU
R/W
R/W
R/W
5
0
5
0
5
0
EOM
EOM
EOM
R/W
R/W
R/W
4
0
4
0
4
0
190
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
XREP
XREP
XREP
R/W
R/W
R/W
3
0
3
0
3
0
ABORT
ABORT
ABORT
R/W
R/W
R/W
2
0
2
0
2
0
THDLCM
THDLCM
THDLCM
R/W
R/W
R/W
1
0
1
0
1
0
October 7, 2003
TRST
TRST
TRST
R/W
R/W
R/W
0
0
0
0
0
0