IDT82P2282 Integrated Device Technology, Inc., IDT82P2282 Datasheet - Page 59

• Manufacturer Part Number: IDT82P2282
• Description: 2 Channel T1/J1/E1 Transceiver
• Manufacturer: Integrated Device Technology, Inc.

IDT82P2282
3.12
ONLY)
format in T1/J1 mode.
the F-bit in the ESF format (refer to Table 13). The six ‘X’s represent the
message. The BOM is declared only when the pattern is matched and
the received message is identical 4 out of 5 consecutive times or 8 out of
10 consecutive times and differs from the previous message. The identi-
fication time is selected by the AVC bit. After a new BOM is declared, the
message is loaded into the BOC[5:0] bits. Every time when the BOC[5:0]
bits are updated, it will be indicated by the BOCI bit. A ‘1’ in the BOCI bit
means there is an interrupt. The interrupt will be reported by the INT pin
if the BOCE bit is ‘1’.
Table 32: Related Bit / Register In Chapter 3.12
Functional Description
The Bit-Oriented Message (BOM) can only be received in the ESF
The BOM pattern is ‘111111110XXXXXX0’ which occupies the DL of
BOC[5:0]
BOCE
BOCI
AVC
Bit
BIT-ORIENTED MESSAGE RECEIVER (T1/J1
BOC Interrupt Indication
BOC Control
RBOC Code
Register
T1/J1 Address (Hex)
081, 181
083, 183
082, 182
48
3.13
ONLY)
deactivate codes only in framed or unframed T1/J1 data stream, and
meets ANSI T1.403 9.3.1.
deactivate code whose length and content are programmed in the
ASEL[1:0]/DSEL[1:0] bits and the ACT[7:0]/DACT[7:0] bits respectively.
In framed mode, the F-bit is selected by the IBCDIDLE bit to compare
with the target activate/deactivate code or not. In unframed mode, all
193 bits are compared with the target activate/deactivate code.
in the received data stream, the Inband Loopback Code Detector keeps
on monitoring the bit error, i.e., the bit differs from the target activate/
deactivate code. If in more than 126 consecutive 39.8ms fixed periods,
less than 600 bit errors are detected in each 39.8ms, the activate/deacti-
vate code is detected and the corresponding LBA/LBD bit will indicate it.
Once more than 600 bit errors are detected in a 39.8ms fixed period, the
activate/deactivate code is out of synchronization and the corresponding
LBA/LBD bit will be cleared. However, even if the F-bit is compared,
whether it is matched or not, the result will not cause bit errors, that is,
the comparison result of the F-bit is discarded.
will set the LBAI/LBDI bit, which means there is an interrupt. The inter-
rupt will be reported by the INT pin if the corresponding LBAE/LBDE bit
is set to ‘1’.
Table 33: Related Bit / Register In Chapter 3.13
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
The Inband Loopback Code Detector tracks the loopback activate/
The received data stream is compared with the target activate/
After four consecutive correct activate/deactivate codes are found
Any transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the LBA/LBD bit
DSEL[1:0]
IBCDIDLE
DACT[7:0]
ASEL[1:0]
ACT[7:0]
LBAE
LBDE
LBAI
LBDI
LBA
LBD
Bit
INBAND LOOPBACK CODE DETECTOR (T1/J1
IBCD Detector Configuration
IBCD Interrupt Indication
IBCD Deactivate Code
IBCD Interrupt Control
IBCD Detector Status
IBCD Activate Code
Register
T1/J1 Address (Hex)
October 7, 2003
07B, 17B
07A, 17A
078, 178
076, 176
079, 179
077, 177