ACS8526LC Semtech Corporation, ACS8526LC Datasheet - Page 10

• Manufacturer Part Number: ACS8526LC
• Description: Line Card Protection Switch for PDH, Sonet or SDH Systems
• Manufacturer: Semtech Corporation

Figure 3 Inactivity and Irregularity Monitoring
Leaky Bucket Timing
The time taken (in seconds) to raise an inactivity alarm on
an SEC that has previously been fully active (Leaky Bucket
empty) will be:
If an input is intermittently inactive then this time can be
longer. The default setting of cnfg_upper_threshold is 6,
therefore the default time is 0.75 s.
The time taken (in seconds) to cancel the activity alarm on
a previously completely inactive SEC is calculated, for a
particular Leaky Bucket, as:
where:
Fast Activity Monitor
Anomalies on the selected clock have to be detected as
they occur and the PLL must be temporarily isolated until
the clock is once again pure. The SEC activity monitor
cannot be used for this because the high degree of
accuracy required dictates that the process be slow. To
achieve the immediacy required, the PLL uses an
alternative mechanism. The phase locked loop itself
contains an additional fast activity monitor such that
Revision 4.01/June 2006 © Semtech Corp.
ADVANCED COMMUNICATIONS
Alarm
Reference
Source
Leaky
Bucket
Response
(cnfg_upper_threshold) / 8
[2
a = cnfg_decay_rate
b = cnfg_bucket_size
c = cnfg_lower_threshold
The default setting is shown in the following:
[2
1
(a)
x (8 - 4)] /8 = 1.0 secs
x (b - c)]/ 8
Inactivities/Irregularities
Programmable Fall Slopes
FINAL
Page 10
within approximately two missing input clock cycles, a
no-activity flag is raised and the DPLL is frozen in Digital
Holdover mode. This flag generates LOS (Loss of Signal)
alarm on pin LOS_ALARM.
With the DPLL in Digital Holdover mode it is isolated from
further disturbances. If the input becomes active again
then the DPLL will continue to lock to the input, with little
disturbance.
Phase Locked Loops (PLLs)
This section is in four parts;
PLL Overview
The PLL circuitry comprises the following blocks shown in
Figure 1: Two Digital PLLs (DPLL1 and DPLL2), two output
multiplying and filtering Analog PLLs (APLL1 and APLL2),
output frequency dividers in an Output Port Frequency
Selection block, a synthesis block, multiplexers MUX1 and
MUX2, and a feedback Analog PLL (APLL3).
These functional blocks, and their interconnections, are
highly configurable, via register control, which provides a
Overview description of the PLLs
Architectural description, introducing the sub-blocks
and their interconnection options for different
frequency selection and jitter filtering
Description of PLL controls- phase error detector
options, Loop bandwidth and damping selection
DPLL summary feature list.
ACS8526 LC/P LITE
(all programmable)
F8530D_026Inact_Irreg_Mon_02
bucket_size
upper_threshold
lower_threshold
DATASHEET
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