ACS8526LC Semtech Corporation, ACS8526LC Datasheet - Page 30

• Manufacturer Part Number: ACS8526LC
• Description: Line Card Protection Switch for PDH, Sonet or SDH Systems
• Manufacturer: Semtech Corporation

Each Register, or register group, is described in the
following Register Map (Table 17) and subsequent
Register Description Tables.
Register Organization
The ACS8526 LC/P LITE uses a total of 46 eight-bit
registers, identified by a Register Name and
corresponding hexadecimal Register Address. They are
presented here in ascending order of Reg. address and
each Register is organized with the most-significant bit
positioned in the left-most bit, with bit significance
decreasing towards the right-most bit. Some registers
carry several individual data fields of various sizes, from
single-bit values (e.g. flags) upwards. Several data fields
are spread across multiple registers, as shown in the
Register Map, Table 17.
Shaded areas in the map are “don’t care” and writing
either 0 or 1 to them will not affect any function of the
device.
Bits labelled “Set to 0” or “Set to 1” must be set as stated
during initialization of the device, either following power-
up, or after a power-on reset (POR). Failure to correctly set
these bits may result in the device operating in an
unexpected way.
CAUTION! Do not write to any undefined register
addresses as this may cause the device to operate in a
test mode. If an undefined register has been
inadvertently addressed, the device should be reset to
ensure the undefined registers are at default values.
Multi-word Registers
For multi-word registers (e.g. Reg. 0C and 0D), all the
words have to be written to their separate addresses, and
without any other access taking place, before their
combined value can take effect. If the sequence is
interrupted, the sequence of writes will be ignored.
Reading a multi-word address freezes the other address
words of a multi-word address so that the bytes all
correspond to the same complete word
Revision 4.01/June 2006 © Semtech Corp.
Register Map
ADVANCED COMMUNICATIONS
FINAL
Page 30
Register Access
Most registers are either configuration registers or status
registers, the exceptions being the chip_id and
chip_revision registers. Configuration registers may be
written to or read from at any time (the complete 8-bit
register must be written, even if only one bit is being
modified). All status registers may be read at any time. A
description of each register is given in the Register Map,
and Register Map Description.
Configuration Registers
Each configuration register reverts to a default value on
power-up or following a reset. Most default values are
fixed, but some will be pin-settable. All configuration
registers can be read out over the serial port.
Status Registers
The Status Registers contain readable registers. They may
all be read from outside the chip but are not writeable
from outside the chip (except for a clearing operation). All
status registers are read via shadow registers to avoid
data hits due to dynamic operation. Each individual status
register has a unique location.
Flags
In the event of loss of the currently selected input a
no-activity flag is raised on pin LOS_ALARM indicating that
the input to DPLL1 has failed. The active state (High or
Low) of the LOS_ALARM pin is programmable and the pin
can either be driven, or set to high impedance when non-
active (Reg 7D refers).
Defaults
Each Register is given a defined default value at reset and
these are listed in the Map and Description Tables.
However, some read-only status registers may not
necessarily show the same default values after reset as
those given in the tables. This is because they reflect the
status of the device which may have changed in the time
it takes to carry out the read, or through reasons of pin
configuration. In the same way, the default values given
for shaded areas could also take different values to those
stated.
ACS8526 LC/P LITE
DATASHEET
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