ACS8526LC Semtech Corporation, ACS8526LC Datasheet - Page 31

• Manufacturer Part Number: ACS8526LC
• Description: Line Card Protection Switch for PDH, Sonet or SDH Systems
• Manufacturer: Semtech Corporation

Table 17 Register Map
Revision 4.01/June 2006 © Semtech Corp.
ADVANCED COMMUNICATIONS
RO = Read Only
R/W = Read/Write
chip_id (RO)
chip_revision (RO)
test_register1 (R/W)
sts_current_DPLL_frequency [7:0] 0C 00
sts_reference_sources (RO)
Alarm Status on inputs:SEC1 & 2
cnfg_ref_source_frequency SEC1
(R/W)
cnfg_input_mode (R/W)
cnfg_DPLL2_path (R/W)
cnfg_dig_outputs_sonsdh (R/W)
cnfg_digtial_frequencies (R/W)
cnfg_differential_output (R/W)
cnfg_auto_bw_sel
cnfg_nominal_frequency
(R/W)
cnfg_DPLL_freq_limit (R/W) [7:0] 41 FF
cnfg_DPLL_freq_limit (R/W) [9:8]
cnfg_freq_divn (R/W)
cnfg_registers_source_select
(R/W)
cnfg_freq_lim_ph_loss
cnfg_upper_threshold (R/W)
cnfg_lower_threshold (R/W)
cnfg_bucket_size (R/W)
cnfg_decay_rate (R/W)
cnfg_output_frequency(R/W) (O2) 61 0A
cnfg_DPLL2_frequency (R/W)
cnfg_DPLL1_frequency (R/W)
cnfg_DPLL2_bw (R/W)
cnfg_DPLL1_locked_bw (R/W)
cnfg_DPLL1_acq_bw (R/W)
cnfg_DPLL2_damping (R/W)
cnfg_DPLL1_damping (R/W)
cnfg_DPLL2_PD2_gain (R/W)
cnfg_DPLL1_PD2_gain (R/W)
cnfg_phase_loss_fine_limit (R/W) 73 A2
cnfg_phase_loss_coarse_limit
(R/W)
cnfg_ip_noise_window (R/W)
cnfg_sync_pulses (R/W)
cnfg_LOS_alarm (R/W)
cnfg_protection (R/W)
(RO)
Register Name
(MFrSync/FrSync) 63 C0 MFrSync_en
[18:16] 07 00
[15:8] 0D 00
[15:8] 3D 99
[13:8] 47 3F
SEC2 23 00 divn_SEC2
[7:0]. 46 FF
[7:0] 3C 99
(O1) 62 00
00 4E
01 21
02 00
03 14 Phase_alarm
11 22
22 00 divn_SEC1
34 C2 auto_extsync_
35 40
38 14
39 08
3A
3B 98 auto_BW_sel
42 03
4B 00
4D
50 06
51 04
52 08
53 01
64 00
65 01
66 00
67 10
69 11
6A
6B 14
6C C2 DPLL2_PD2_
6D C2 DPLL1_PD2_
74 E5
76 06 ip_noise_
7A
7D 02
7E
C2
13
00 2k_8k_from_
85
(RO)
en
freq_lim_ph_
loss
gain_enable
gain_enable
fine_limit_en
coarse_lim_
phaseloss_en
window_en
DPLL2
7 (msb)
digital2_frequency
Disable_180
lock8k_SEC1
lock8k_SEC2
dig2_sonsdh
FrSync_en
APLL2_for_
DPLL1_E1/
DS1
noact_ph_loss
wide_range_
en
6
output_freq_O1
DPLL1_PD2_gain_alog_8k
DPLL2_PD2_gain_alog
DPLL1_PD2_gain_alog
lower_threshold_value (Activity alarm, Leaky Bucket - reset threshold)
upper_threshold_value (Activity alarm, Leaky Bucket - set threshold)
No Activity
SEC2
XO_ edge
dig1_sonsdh
narrow_en
multi_ph_resp
FINAL
Page 31
DPLL1_freq_to_APLL2
bucket_size_value (Activity alarm, Leaky Bucket - size)
5
digital1_frequency
divn_value [7:0] (divide Input frequency by n)
Bits [15:8] of sts_current_DPLL_frequencyy
Bits [7:0] of sts_current_DPLL_frequency
Bits[15:8] of cnfg_nominal_frequency
Bits[7:0] of cnfg_nominal_frequency
Bits[7:0] of cnfg_DPLL_freq_limit
chip_id[15:8], 8 MSBs of Chip ID
Resync_
analog
DPLL1_DPLL2
_select
chip_id[7:0], 8 LSBs of Chip ID
4
chip_revision[7:0]
protection_value
divn_value [13:8] (divide Input frequency by n)
Data Bit
Set to 0
DPLL1_lim_int
8k_invert
3
ACS8526 LC/P LITE
reference_source_frequency_SEC1
reference_source_frequency_SEC2
8K Edge
Polarity
ip_sonsdhb
8k_pulse
LOS_GPO_en
Bits [18:16] of sts_current_DPLL_frequency
phase_loss_coarse_limit
2
output_freq_O2
DPLL2_PD2_gain_digital
DPLL1_PD2_gain_digital
phase_loss_fine_limit
DPLL2_frequency
DPLL1_frequency
DPLL2_damping
DPLL1_damping
Set to 0
No Activity
SEC1
Bits[9:8] cnfg_DPLL_freq_limit
2k_invert
LOS_tristate_
en
alarm, Leaky Bucket - leak rate)
DPLL1_acquisition_bandwidth
decay_rate_value (Activity
DPLL1_locked_bandwidth
Output O1 _LVDS_PECL
1
DPLL2_bandwidth
DATASHEET
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Set to 0
2k_pulse
LOS_
polarity
0 (lsb)