MSC8156 Freescale Semiconductor, Inc, MSC8156 Datasheet

MSC8156

Manufacturer Part Number

MSC8156

Description

Six-core Digital Signal Processor

Manufacturer

Freescale Semiconductor, Inc

Datasheet

1.MSC8156.pdf (68 pages)

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Data Sheet: Product Preview

Six-Core Digital Signal

Processor

• Six StarCore SC3850 DSP subsystems, each with an SC3850 DSP

• Chip-level arbitration and switching system (CLASS) that

• 1056 Kbyte 128-bit wide M3 memory, 1024 Kbytes of which can

• 96 Kbyte boot ROM.

• Three input clocks (one global and two differential).

• Five PLLs (three global and two Serial RapidIO PLLs).

• Multi-Accelerator Platform Engine for Baseband (MAPLE-B)

• Two DDR controllers with up to a 400 MHz clock (800 MHz data

• DMA controller with 32 unidirectional channels supporting 16

• Up to four independent TDM modules with programmable word

This document contains information on a product under development. Freescale reserves

the right to change or discontinue this product without notice.

core, 32 Kbyte L1 instruction cache, 32 Kbyte L1 data cache,

unified 512 Kbyte L2 cache configurable as M2 memory in

64 Kbyte increments, memory management unit (MMU),

extended programmable interrupt controller (EPIC), two

general-purpose 32-bit timers, debug and profiling support,

low-power Wait, Stop, and power-down processing modes, and

ECC/EDC support.

provides full fabric non-blocking arbitration between the cores

and other initiators and the M2 memory, shared M3 memory,

DDR SRAM controllers, device configuration control and status

registers, MAPLE-B, and other targets.

be turned off to save power.

with a programmable system interface, Turbo decoding, Viterbi

decoding, and FFT/iFFT and DFT/iDFT processing. MAPLE-B

can be disabled when not required to reduce overall power

consumption.

rate), 64/32 bit data bus, supporting up to a total 2 Gbyte in up to

four banks (two per controller) and support for DDR2 and DDR3.

memory-to-memory channels with up to 1024 buffer descriptors

per channel, and programmable priority, buffer, and multiplexing

configuration. It is optimized for DDR SDRAM.

size (2, 4, 8, or 16-bit), hardware-base A-law/μ-law conversion,

up to 62.5 Mbps data rate for each TDM link, and with glueless

interface to E1 or T1 framers that can interface with

H-MVIP/H.110 devices, TSI, and codecs such as AC-97.

• High-speed serial interface that supports two Serial RapidIO

• QUICC Engine technology subsystem with dual RISC

• I/O Interrupt Concentrator consolidates all chip maskable

• UART that permits full-duplex operation with a bit rate of up to

• Two general-purpose 32-bit timers for RTOS support per SC3850

• Eight programmable hardware semaphores.

• Up to 32 virtual interrupts and a virtual NMI asserted by simple

• I

• Up to 32 GPIO ports, sixteen of which can be configured as

• Boot interface options include Ethernet, Serial RapidIO interface,

• Supports standard JTAG interface

• Low power CMOS design, with low-power standby and

• 45 nm SOI CMOS technology.

interfaces, one PCI Express interface, and two SGMII interfaces

(multiplexed). The Serial RapidIO interfaces support 1x/4x

operation up to 3.125 Gbaud with a single messaging unit and two

DMA units. The PCI Express controller supports 32- and 64-bit

addressing, x4, x2, and x1 link.

processors, 48 Kbyte multi-master RAM, 48 Kbyte instruction

RAM, supporting two communication controllers for two Gigabit

Ethernet interfaces (RGMII or SGMII), to offload scheduling

tasks from the DSP cores, and an SPI.

interrupt and non-maskable interrupt sources and routes then to

INT_OUT, NMI_OUT, and the cores.

6.25 Mbps.

core, four timer modules with four 16-bit fully programmable

timers, and eight software watchdog timers (SWT).

write access.

external interrupts.

power-down modes, and optimized power-management circuitry.

C interface.

C, and SPI.

MSC8156

Document Number: MSC8156

FC-PBGA–783

29 mm × 29 mm

Rev. 1, 12/2010

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