L64767 LSI Logic Corporation, L64767 Datasheet - Page 5

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L64767

Manufacturer Part Number
L64767
Description
Smatv Qam Encoder
Manufacturer
LSI Logic Corporation
Datasheet
Functional Description
Input Synchronizer
This section provides a brief description of the major blocks shown in
Figure
As shown in
clock. All other processing is done based on the OCLK. OCLK can be
two or four times the symbol clock (SCLK) frequency based on the
oversampling setting of the Nyquist filter.
ICLK is limited to a maximum of 62.5 MHz in serial input mode and
10 MHz in parallel input mode. The maximum symbol rate handled by
the L64767 is 7.5 Mbaud. Therefore, OCLK is limited to 15 MHz in 2-fold
oversampling mode and 30 MHz in 4-fold oversampling mode.
The input format for the L64767 is based on the data format specified in
the MPEG-2 system layer standard in relation to the DVB transport
framing structure. It requires a Reed-Solomon (204,188) protected
transport packet to consist of 204 bytes, including the sync byte plus
187 data bytes and 16 redundancy bytes.
This basic format has been adopted by the V4/MOD-B task force for a
multiprogram TV via satellite standard, and by the DVB group in Europe.
In a scrambled DVB data stream, one out of every eight synchronization
words is mod 2 complemented (inverted) in order to define the beginning
of a scrambling sequence.
The descrambled stream contains no inverted sync word. This MPEG-2
frame format is the basic input format for the L64767 device. The device
assumes that the inserted sync byte at the chip input can only have the
normal value, not the inverted one. You can insert gaps for Reed-Solomon
check bytes or make them available in the input stream.
To synchronize input, you can do one of the following:
L64767 SMATV QAM Encoder
Send a frame start pulse at the FSTARTIN pin forcing the beginning
of each Reed-Solomon code block. Whenever FSTARTIN is
asserted, the L64767 reinserts the sync byte into the data stream
and inverts the sync word every eight blocks, as defined by the DVB.
2.
Figure
2, only the input synchronizer is driven by the input
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