XRP7714 Exar, XRP7714 Datasheet - Page 13

• Manufacturer Part Number: XRP7714
• Description: Quad Channel Digital PWM Step Down Controller
• Manufacturer: Exar

I
When the ENABLE pin is set, internal VCC and VDD power up upon the power up of VIN1. Once the
bandgap reference is stable and VCC and VDD fall into the acceptable range, an internal VDDOK
flag is generated. A SYS_RESET remains low for a few clock cycles to reset all the internal
registers. After that the internal CONFIGURATION_TRANSFER signal raises high and the chip
transits to the second phase.
C
In this phase, the contents in the configuration memory are transferred to the internal registers.
The internal oscillator switches to the programed switching frequency. The GPIO pins are properly
configured as either inputs or outputs. If the chip is programmed to run in the I
and GPIO5 are configured to serve as SDA and SCL for the I
the NON-I
C
In this phase, the chip is ready for normal operation. An internal CHIP_READY flag goes high and
enables the I
always-on channels are enabled. Channels that are configured to be enabled by GPIOs are also
enabled if the respective GPIO is asserted.
S
This 100mA low drop-out regulator can be programmed as 3.3V or 5V in SET_STBLDO_EN_CONFIG
register. Its output is seen on the LDOOUT Pin. This LDO is fully controllable via the Enable Pin
(configured to turn on as soon as power is applied), a GPIO, and/or I
The 5V output setting of the regulator is only available if VIN1 is above 6.5V, and the 3.3V output
setting is available for the entire VIN1 range from 4.75 to 25V.
E
The XRP7714 is enabled via raising the ENABLE Pin high.
lowering the same ENABLE Pin.
SOFTRESET Command.
© 2010 Exar Corporation
NTERNAL
NABLING
ONFIGURATION
HIP
TANDBY
R
EADY
2
L
, D
C mode, then these two pins can be used as GPIO4 and GPIO5 respectively.
LDO P
OW
P
ISABLING AND
2
C to acknowledge the Host’s serial commands. Channels that are configured as
HASE
D
ROP
T
OWER
RANSFER
– P
-
ENABLE_PIN
VIN1
VCC
VDD
VDDOK
SYS_RESET
CONFIG_TRANSFER
CHIP_READY
OUT
-U
HASE
P
R
P
EGULATOR
P
R
HASE
3
HASE
ESET
Phase 1
Q
Q
There is also the capability for resetting the Chip via an I
– P
u
u
– P
a
a
Fig. 21: Power Up Sequence
d
d
HASE
HASE
C
C
h
h
a
a
1
2
13/27
n
n
Phase 2
n
n
e
e
l
l
D
D
i
i
g
g
i
i
t
t
a
2
a
C bus. If chip is programmed to run in
l
Phase 3
l
P
P
The chip can then be disabled by
W
W
M
M
2
C communication.
S
S
t
t
e
e
p
p
D
D
o
o
w
w
2
n
C mode, GPIO4
n
www.DataSheet4U.com
X
X
C
C
R
R
o
o
P
n
P
n
Rev. 1.1.3
t
t
7
7
r
r
o
o
7
7
l
l
1
1
l
l
e
e
2
4
4
C
r
r