AD9516-3 Analog Devices, AD9516-3 Datasheet - Page 17

• Manufacturer Part Number: AD9516-3
• Description: 14-Output Clock Generator
• Manufacturer: Analog Devices

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 20. Pin Function Descriptions
Pin No.
1, 11, 12, 30, 31,
32, 38, 49, 50, 51,
57, 60, 61
2
3
4
5
6
7
8
9
10
13
14
15, 18, 19, 20
16
17
21
22
23
24
27, 41, 54
37, 44, 59, EPAD
56
Mnemonic
VS
REFMON
LD
VCP
CP
STATUS
REF_SEL
SYNC
LF
BYPASS
CLK
CLK
NC
SCLK
CS
SDO
SDIO
RESET
PD
VS_LVPECL
GND
OUT0
NC = NO CONNECT
REF_SEL
REFMON
BYPASS
STATUS
Description
3.3 V Power Pins.
Reference Monitor (Output). This pin has multiple selectable outputs; see Table 53 0x1B.
Lock Detect (Output). This pin has multiple selectable outputs; see Table 53 0x1A.
Power Supply for Charge Pump (CP); V
Charge Pump (Output). Connects to external loop filter.
Status (Output). This pin has multiple selectable outputs; see Table 53 0x17.
Reference Select. Selects REF1 (low) or REF2 (high). This pin has an internal 30 kΩ pull-down resistor.
Manual Synchronizations and Manual Holdover. This pin initiates a manual synchronization and is
also used for manual holdover. Active low. This pin has an internal 30 kΩ pull-up resistor.
Loop Filter (Input). Connects to VCO control voltage node internally.
This pin is for bypassing the LDO to ground with a capacitor.
Along with CLK, this is the differential input for the clock distribution section.
Along with CLK, this is the differential input for the clock distribution section.
No Connection.
Serial Control Port Data Clock Signal.
Serial Control Port Chip Select; Active Low. This pin has an internal 30 kΩ pull-up resistor.
Serial Control Port Unidirectional Serial Data Out.
Serial Control Port Bidirectional Serial Data In/Out.
Chip Reset; Active Low. This pin has an internal 30 kΩ pull-up resistor.
Chip Power Down; Active Low. This pin has an internal 30 kΩ pull-up resistor.
Extended Voltage 2.5 V to 3.3 V LVPECL Power Pins.
Ground Pins; Includes External Paddle (EPAD).
LVPECL Output; One Side of a Differential LVPECL Output.
SYNC
SCLK
VCP
CLK
CLK
CP
NC
VS
LD
VS
VS
LF
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
PIN 1
INDICATOR
Figure 6. Pin Configuration
Rev. 0 | Page 17 of 84
(Not to Scale)
AD9516-3
TOP VIEW
LVPECL LVPECL
LVPECL LVPECL
S
< V
CP
< 5.0 V.
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
OUT6 (OUT6A)
OUT6 (OUT6B)
OUT7 (OUT7A)
OUT7 (OUT7B)
GND
OUT2
OUT2
VS_LVPECL
OUT3
OUT3
VS
GND
OUT9 (OUT9B)
OUT9 (OUT9A)
OUT8 (OUT8B)
OUT8 (OUT8A)
AD9516-3