AD9850 Analog Devices, AD9850 Datasheet - Page 11

• Manufacturer Part Number: AD9850
• Description: CMOS/ 125 MHz Complete DDS Synthesizer
• Manufacturer: Analog Devices

REV. E
COS OUT
REF CLK
DAC STROBE
Figure 20. Parallel-Load Power-Down Sequence/Internal Operation
RESET
DATA (W0)
Figure 21. Parallel-Load Power-Up Sequence/Internal Operation
DATA (W0)
REF CLK
REF CLK
W CLK
FQ UD
W CLK
FQ UD
RESULTS OF RESET:
SYMBOL
t
t
t
t
t
RH
RL
RR
RS
OL
Figure 19. Master Reset Timing Sequence
– FREQUENCY/PHASE REGISTER SET TO 0
– ADDRESS POINTER RESET TO W0
– POWER-DOWN BIT RESET TO “0”
– DATA INPUT REGISTER UNEFFECTED
t
RH
DEFINITION
CLK DELAY AFTER RESET RISING EDGE
RESET FALLING EDGE AFTER CLK
RECOVERY FROM RESET
MINIMUM RESET WIDTH
RESET OUTPUT LATENCY
INTERNAL CLOCKS ENABLED
t
RS
XXXXX000
XXXXX100
–11–
t
OL
t
RL
INTERNAL CLOCKS DISABLED
t
RR
MIN SPEC
3.5ns
3.5ns
2 CLK CYCLES
5 CLK CYCLES
13 CLK CYCLES
COS (0)
AD9850