AD9850 Analog Devices, AD9850 Datasheet - Page 8

• Manufacturer Part Number: AD9850
• Description: CMOS/ 125 MHz Complete DDS Synthesizer
• Manufacturer: Analog Devices

AD9850
THEORY OF OPERATION AND APPLICATION
The AD9850 uses direct digital synthesis (DDS) technology, in
the form of a numerically controlled oscillator, to generate a
frequency/phase-agile sine wave. The digital sine wave is con-
verted to analog form via an internal 10-bit high speed D/A
converter, and an onboard high speed comparator is provided to
translate the analog sine wave into a low jitter TTL/CMOS-
compatible output square wave. DDS technology is an innova-
tive circuit architecture that allows fast and precise manipulation
of its output frequency under full digital control. DDS also
enables very high resolution in the incremental selection of
output frequency; the AD9850 allows an output frequency
resolution of 0.0291 Hz with a 125 MHz reference clock ap-
plied. The AD9850’s output waveform is phase-continuous
when changed.
The basic functional block diagram and signal flow of the
AD9850 configured as a clock generator is shown in Figure 16.
The DDS circuitry is basically a digital frequency divider function
whose incremental resolution is determined by the frequency of
the reference clock divided by the 2
tuning word. The phase accumulator is a variable-modulus
counter that increments the number stored in it each time it
IF IN
PROCESSOR
Rx
Figure 13. Basic AD9850 Clock Generator Application
with Low-Pass Filter
Figure 14. AD9850 Clock Generator Application in a
Spread-Spectrum Receiver
VCA
XTAL
OSC
LOCKED TO Tx CHIP/
REFERENCE
SYMBOL PN RATE
125MHz
CLOCK
DATA
LOW-PASS
BUS
I/Q MIXER
FILTER
AND
FREQUENCY
ADC CLOCK
8-b
OR 1-b
RESET, AND 2
CLOCK LINES
CLK
Q
5 PARALLEL DATA,
I
+V
AD9850
GENERATOR
DUAL 8-BIT
S
AD9059
40 SERIAL DATA,
AD9850
CLOCK
ADC
RSET
ADC ENCODE
GND
QOUTB
IOUTB
QOUT
8
8
IOUT
VINN
VINP
CHIP/SYMBOL/PN
32
N
RATE DATA
DEMODULATOR
number of bits in the
100k
100k
DIGITAL
COMP
OUTPUTS
CLOCK
CMOS
5-POLE ELLIPTICAL
42MHz LOW-PASS
200
200
100
470pF
AGC
LOW-PASS
FILTER
IMPEDANCE
Rx
BASEBAND
DIGITAL
DATA
OUT
TRUE
200
–8–
receives a clock pulse. When the counter overflows it wraps
around, making the phase accumulator’s output contiguous.
The frequency tuning word sets the modulus of the counter that
effectively determines the size of the increment (∆ Phase) that
gets added to the value in the phase accumulator on the next
clock pulse. The larger the added increment, the faster the ac-
cumulator overflows, which results in a higher output fre-
quency. The AD9850 uses an innovative and proprietary
algorithm that mathematically converts the 14-bit truncated
value of the phase accumulator to the appropriate COS value.
This unique algorithm uses a much reduced ROM look-up table
and DSP techniques to perform this function, which contributes
to the small size and low power dissipation of the AD9850. The
relationship of the output frequency, reference clock, and tuning
word of the AD9850 is determined by the formula:
where: ∆ Phase = value of 32-bit tuning word
The digital sine wave output of the DDS block drives the inter-
nal high speed 10-bit D/A converter that reconstructs the sine
c. Digitally-Programmable ”Divide-by-N“ Function in PLL
REFERENCE
125MHz
CLOCK
Frequency Up-Conversion Applications
Figure 15. AD9850 Complete-DDS Synthesizer in
FREQUENCY
FREQUENCY
b. Frequency/Phase–Agile Reference for PLL
CLKIN = input reference clock frequency in MHz
f
OUT
a. Frequency/Phase–Agile Local Oscillator
REFERENCE
REF
COMPLETE-
FILTER
125MHz
AD9850
TUNING
= frequency of the output signal in MHz
WORD
DDS
IN
IF
f
OUT
COMPARATOR
TUNING WORD
COMPLETE-
AD9850
= (∆ Phase × CLKIN)/2
FILTER
PHASE
COMPLETE-DDS
DDS
AD9850
FILTER
COMPARATOR
DIVIDE-BY-N
PROGRAMMABLE
“DIVIDE-BY-N”
PHASE
FILTER
LOOP
FUNCTION
FILTER
TUNING
WORD
VCO
FILTER
LOOP
32
RF
FREQUENCY
OUT
FREQUENCY
OUT
RF
VCO
FREQUENCY
OUT
REV. E
RF