AD9851 Analog Devices, AD9851 Datasheet - Page 21

• Manufacturer Part Number: AD9851
• Description: CMOS 180 MHz DDS/DAC Synthesizer
• Manufacturer: Analog Devices

Figure 34. Typical CMOS comparator p-p output jitter
with the AD9851 configured as a clock generator, DDS f
= 70.1 MHz, V
LPF. Graph details the center portion of a rising edge with
scope in delayed trigger mode, 200 ps/div. Cursors show
280 ps p-p jitter.
Figure 35. Output Phase Noise (5.2 MHz A
Multiplier Enabled, System Clock = 180 MHz, Reference
Clock = 30 MHz
Figure 36. Output Residual Phase Noise (5.2 MHz A
6 REFCLK Multiplier Disabled, System Clock = 180 MHz,
Reference Clock = 180 MHz
REV. C
1
Tek Run 4.00GS/s
–100
–115
–120
–125
–130
–135
–140
–145
–120
–125
–130
–135
–140
–145
–150
–155
Ch1 200mV
100
100
@ : 2.668ns
: 280ps
S
= +5 V, system clock = 180 MHz, 70 MHz
Sample
FREQUENCY OFFSET – Hz
FREQUENCY OFFSET – Hz
1k
1k
T
[
AD9851 RESIDUAL PHASE NOISE
]
M 12.5ns Ch 1
D 200ps Runs After
AD9851 PHASE NOISE
10k
10k
OUT
–200mV
), 6 REFCLK
100k
100k
OUT
),
OUT
–21–
Figure 37. Spurious-free dynamic range (SFDR) is gener-
ally a function of the DAC analog output frequency. Ana-
log output frequencies of 1/3 the system clock rate are
considered worst case. Plotted below are typical worst
case SFDR numbers for various system clock rates.
Figure 38. Comparator Rise Time, 15 pF Load
1
1
Figure 39. Comparator Fall Time, 15 pF Load
Tek Stop 2.50GS/s
Tek Stop 2.50GS/s
75
70
65
60
55
50
45
Ch1 100mV
Ch1 100mV
@ : 105.2ns
10
: 2.0ns
C1 Rise
2.03ns
20
V
SYSTEM CLOCK FREQUENCY – MHz
S
= +5V
40
60
2227 Acgs
T
T [
22 Acgs
V
S
FUNDAMENTAL OUTPUT =
SYSTEM CLOCK/3
80
= +3.3V
[
]
]
100
M 20.0ns Ch 1
D 5.00ns Runs After
M 20.0ns Ch 1
D 5.00ns Runs After
120 140
@ : 103.6ns
: 2.3ns
C1 Fall
2.33ns
AD9851
160
252mV
252mV
180