AD9851 Analog Devices, AD9851 Datasheet - Page 3

• Manufacturer Part Number: AD9851
• Description: CMOS 180 MHz DDS/DAC Synthesizer
• Manufacturer: Analog Devices

Parameter
TIMING CHARACTERISTICS
CMOS LOGIC INPUTS
POWER SUPPLY
NOTES
1
2
3
4
5
6
Specifications subject to change without notice.
REV. C
+V
Indicates the minimum signal levels required to reliably clock the device at the indicated supply voltages. This specifies the p-p signal level and dc offset needed when
The comparator’s jitter contribution to any input signal. This is the minimum jitter on the outputs that can be expected from an ideal input. Considerably more
Timing of input signals FQ_UD, WCLK, RESET are asynchronous to the Reference Clock; however, the presence of a Reference Clock is required to implement
Not applicable when 6 REFCLK Multiplier is engaged.
Assumes no capacitive load on DACBP (Pin 17).
the clocking signal is not of CMOS/TTL origin, i.e., a sine wave with 0 V dc offset.
output jitter is seen when nonideal input signals are presented to the comparator inputs. Nonideal characteristics include the presence of extraneous, nonharmonic
signals (spur’s, noise), slower slew rate and low comparator overdrive.
those functions. In the absence of a Reference Clock, the AD9851 automatically enters power-down mode rendering the IC, including the comparator, inoperable
until a Reference Clock is restored. Very high speed updates of frequency/phase word will require FQ_UD and WCLK to be externally synchronized with the exter-
nal Reference Clock to assure proper timing.
t
t
t
t
t
t
t
t
t
t
t
Wake-Up Time from Power-Down Mode
Logic “1” Voltage, +5 V Supply
Logic “1” Voltage, +3.3 V Supply
Logic “1” Voltage, +2.7 V Supply
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Rise/Fall Time
Input Capacitance
V
Power Dissipation @ :
P
WH
DS
FH
CD
FD
CF
RH
RL
RR
RS
OL
S
S
DISS
collectively refers to the positive voltages applied to DVDD, PVCC and AVDD. Voltages applied to these pins should be of the same potential.
Frequency Change
Phase Change
62.5 MHz Clock, +2.7 V Supply
100 MHz Clock, +2.7 V Supply
62.5 MHz Clock, +3.3 V Supply
125 MHz Clock, +3.3 V Supply
62.5 MHz Clock, +5 V Supply
125 MHz Clock, +5 V Supply
180 MHz Clock, +5 V Supply
62.5 MHz Clock, +5 V Supply
62.5 MHz Clock, +3.3 V Supply
62.5 MHz Clock, +2.7 V Supply
100 MHz Clock, +2.7 V Supply
125 MHz Clock, +5 V Supply
125 MHz Clock, +3.3 V Supply
180 MHz Clock, +5 V Supply
+5 V Supply
+2.7 V Supply
6
, t
, t
(Minimum RESET Width)
(RESET Falling Edge After CLKIN)
, t
(Output Latency from FQ_UD)
(Recovery from RESET)
(RESET Output Latency)
(REFCLK Delay After FQ_UD)
(FQ_UD Min Delay After W_CLK)
(CLKIN Delay After RESET Rising Edge)
Current @:
DH
FL
WL
Power-Down Mode @:
(FQ_UD Min Pulsewidth High/Low)
(Data to W_CLK Setup and Hold Times)
(W_CLK Min Pulsewidth High/Low)
4
5
6
Temp
FULL
FULL
FULL
FULL
FULL
FULL
FULL
FULL
FULL
FULL
FULL
FULL
+25 C
+25 C
+25 C
+25 C
+25 C
+25 C
+25 C
+25 C
+25 C
+25 C
+25 C
+25 C
+25 C
+25 C
+25 C
+25 C
+25 C
+25 C
+25 C
+25 C
+25 C
+25 C
+25 C
+25 C
+25 C
–3–
Test
Level
IV
IV
IV
IV
IV
IV
IV
IV
V
I
I
I
I
I
I
IV
V
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
IV
IV
IV
IV
Min
3.5
3.5
7
3.5
7
18
13
3.5
3.5
2
5
13
3.5
3.0
2.4
AD9851BRS
Typ
5
3
30
40
35
55
50
70
110
250
115
85
110
365
180
555
17
4
Max
0.4
12
12
100
35
50
45
70
65
90
130
325
150
95
135
450
230
650
55
20
Units
ns
ns
ns
Cycles
Cycles
ns
Cycles
Cycles
Cycles
V
V
V
V
ns
pF
mA
mA
mA
mA
mA
mA
mW
mW
mW
ns
ns
SYSCLK
SYSCLK
ns
SYSCLK
SYSCLK
SYSCLK
mA
mW
mW
mW
mW
mW
mW
AD9851
s
A
A