AD9854 Analog Devices, AD9854 Datasheet - Page 10
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AD9854
Manufacturer Part Number
AD9854
Description
CMOS 300 MHz Quadrature Complete-DDS
Manufacturer
Analog Devices
Datasheet
1.AD9854.pdf
(44 pages)
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AD9854
Figures 14 and 15 show the effects of utilizing “sweet spots” in the tuning range of a DDS. Figure 14 represents a tuning word that
accentuates the aberrations associated with truncation in the DDS algorithm. Figure 16 is essentially the same output frequency (a
few tuning codes over), but it displays much fewer spurs on the output due to the selection of a tuning “sweet spot.” Consideration
should be given to all DDS applications to exploit the benefit of sweet spot tuning.
Figure 14. The Opposite of a “Sweet Spot.” 112.469 MHz
with multiple high energy spurs close around the
fundamental.
Figures 16 and 17 show the narrowband performance of the AD9854 when operating with a 20 MHz reference clock and the
REFCLK Multiplier enabled at 10 vs. a 200 MHz external reference clock.
Figure 16. Narrowband SFDR, 39.1 MHz, 50 kHz BW,
200 MHz EXTCLK with REFCLK Multiplier Bypassed
–100
–100
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
0
CENTER 112.499MHz
CENTER 39.1MHz
50kHz/
5kHz/
SPAN 500kHz
SPAN 50kHz
–10–
spurs shifted out-of-band.
dramatically better results. 112.499 MHz with all
Figure 15. A slight change in tuning word yields
Figure 17. Narrowband SFDR, 39.1 MHz, 50 kHz BW,
10 MHz EXTCLK with REFCLK Multiplier = 10
–100
–100
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
0
CENTER 112.469MHz
CENTER 39.1MHz
50kHz/
5kHz/
SPAN 500kHz
SPAN 50kHz
REV. 0