AD9854 Analog Devices, AD9854 Datasheet - Page 30

• Manufacturer Part Number: AD9854
• Description: CMOS 300 MHz Quadrature Complete-DDS
• Manufacturer: Analog Devices

AD9854
MSB/LSB TRANSFERS
The AD9854 serial port can support both most significant bit
(MSB) first or least significant bit (LSB) first data formats. This
functionality is controlled by Bit 1 of serial register bank 20h.
When this bit is set active high, the AD9854 serial port is in LSB
first format. This bit defaults low, to the MSB first format. The
instruction byte must be written in the format indicated by Bit 1
of serial register bank 20h. That is, if the AD9854 is in LSB first
mode, the instruction byte must be written from least significant
bit to most significant bit.
Update Clock Operation
Programming the AD9854 is asynchronous to the system clock
with all data being stored in a buffer memory that does not
immediately affect the part operation. The buffer memory is
transferred to the register bank synchronous to system clock.
The register bank information affects part operation.
This transfer of data can occur automatically, with frequency of
updates programmable by the user, or can occur completely under
user control.
Complete user control, referred to as external update mode,
allows the user to drive the I/O UD signal from their ASIC or
DSP. The AD9854 I/O UD pin is configured as an input in
external update mode. A rising edge on I/O UD indicates to
the AD9854 that the contents of the buffer memory is to be
transferred to the register bank. The design uses an edge detector
to signal the AD9854 to transfer data which allows a very small
minimum high pulse width requirement (two system clock peri-
ods). Its important to note that if the user keeps I/O UD high,
the AD9854 will NOT continuously update the register bank.
SCLK
SDIO
CS
SCLK
SDIO
SDO
CS
10
10
11
11
IR WRITE PHASE
12
IR WRITE PHASE
12
13
Figure 56. Data Read Cycle, 3-Wire Configuration, SCLK Idle Low
13
14
14
15
15
16
Figure 55. Data Write Cycle, SCLK Idle High
16
17
17
B0
B0
B1
B1
B2
–30–
B2
B3
B3
Internal update mode, in which the AD9854 transfers data from
the buffer memory to the register bank automatically, configures
the AD9854 I/O UD pin as an output. The AD9854 generates a
high pulse on I/O UD pin to signal the user that the buffer memory
has just been transferred to the register bank. The minimum
high pulsewidth is designed to be eight system clock cycles (min).
The I/O UD signal can be used as an interrupt within the system.
Its important to note that as an output I/O UD pin will not have
anything approaching a 50/50 duty cycle for slower update rates.
Programming the Update Clock register for values less than five
will cause the I/O UD pin to remain high. The update clock func-
tionality still works, its just that the user cannot use the signal as
an indication that data is transferring. This is an affect of the
minimum high pulse time when I/O UD is an output.
For internal update clock operation, the rate which the updates
occur is programmed into the update clock register. The update
clock register is 32 bits and the value written into the register
corresponds to HALF the number of clock cycles between updates.
That is, if a value of 00_00_00_0A (hex), is written into the update
clock register the rising edge of the I/O UD pin will occur every
20 cycles (0A hex equals 10 decimal).
CONTROL REGISTER
The Control Register is located in the shaded portion of the
Table V at address 1D through 20 hex. It is composed of 32
bits. Bit 31 is located at the top left position and Bit 0 is located
in the lower right position of the shaded table portion. The reg-
ister has been subdivided below to make it easier to locate the
text associated with specific control categories.
DATA TRANSFER – TWO BYTE READ
B4
B4
DATA TRANSFER – TWO BYTE WRITE
B5
B5
B6
B6
B7
B7
B8
B8
B9
B9
B10
B10
B11
B11
B12
B12
B13
B13
B14
B14
B15
B15
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