AD9854 Analog Devices, AD9854 Datasheet - Page 24

• Manufacturer Part Number: AD9854
• Description: CMOS 300 MHz Quadrature Complete-DDS
• Manufacturer: Analog Devices

AD9854
2. Stop using the hold pin function, then ramp-down the output
3. Stop and abruptly terminate the transmission using the CLR
4. Continue chirp by reversing direction and returning to the
5. Continue chirp by immediately returning to the F1 beginning
BPSK (Mode 100)
Binary, biphase or bipolar phase shift keying is a means to rapidly
select between two preprogramming 14-bit output phase offsets
that will identically affect both the I and Q outputs of the AD9854.
The logic-state of Pin 29, BPSK pin, controls the selection of
Phase Adjust register number 1 or 2. When low, Pin 29 selects
Phase Adjust register 1; when high, Phase Adjust register 2 is
selected. Figure 48 illustrates phase changes made to four cycles
of an output carrier.
Basic BPSK programming steps:
1. Program a carrier frequency into Frequency Tuning Word 1.
2. Program appropriate 14-bit phase words in Phase Adjust
3. Attach BPSK data source to Pin 29.
4. Activate I/O Update pulse when ready.
amplitude using the digital multiplier stages and the Shaped
Keying pin, Pin 30, or via program register control (addresses
21–24 hex).
ACC2 bit.
previous, or another, destination frequency in a linear or user-
directed manner. If this involves going down in frequency, a
negative 48-bit Delta Frequency Word (the MSB is set to
“1”) must be loaded into registers 10–15 hex. Any decreasing
frequency step of the Delta Frequency Word requires the MSB
to be set to logic high.
frequency in a sawtooth fashion and repeat the previous chirp
process again. This is where CLR ACC1 control bit is used.
An automatic, repeating chirp can be setup using the 32-bit
Update Clock to issue CLR ACC1 commands at precise time
intervals. Adjusting the timing intervals or changing the Delta
Frequency Word will change the chirp range. It is incumbent
upon the user to balance the chirp duration and frequency
resolution to achieve the proper frequency range.
registers 1 and 2.
PHASE ADJUST 1
PHASE ADJUST 2
BPSK DATA
MODE
FTW1
000 (DEFAULT)
360
0
0
PHASE AFTER
ONSET
Figure 48. BPSK Mode
PHASE BEFORE
ONSET
–24–
If phase shift keying is not the objective, but rather a broader
range of phase offsets is needed, the user should select the Single
Tone mode and program Phase Adjust register 1 using the serial or
high-speed parallel programming bus.
I/O Port Buffers—100 MHz, 8-bit parallel or 10 MHz serial
loading, SPI-compatible. The programming mode is selected
externally via the serial/parallel (S/P Select) pin. I/O Buffers can
be written to, or read from, according to the signals supplied to
the Read (RDB) and Write pins (WRB) and the 6-bit address
(A0–A5) in the parallel mode or to CSB, SCLK and SDIO pins
in the Serial mode.
Data in the I/O Port Buffers is stored until overwritten by changes
in program instructions supplied by the user or until power is
removed. An I/O Update clocks-in the data from the I/O Buffers
to the DDS Programming Registers where it is executed.
AM—amplitude modulation of the I and Q DACs is possible
using the I/O port to control 12-bit digital multiplier stages that
precede the DACs. The multipliers can also be used to set the
DAC outputs between zero- and full-scale for static amplitude
adjustment. Both I and Q DAC amplitudes are individually
programmable. See the “Shaped On/Off Keying” description
for more information. Shaped keying function does not apply to
the Q DAC when configured as a Control DAC. In this instance,
the user is in control of the Control DAC output level via the
12-bit QDAC register at address 26 and 27 hex of the pro-
gramming registers
High-Speed Comparator—optimized for high speed, >300 MHz
toggle rate, low jitter, sensitive input, built-in hysteresis and
an output level of 1 V p-p minimum into 50
levels into high impedance loads. The comparator can be sepa-
rately powered down to conserve power. This comparator is used
in “clock generator” applications to square up a bandpass or
low-pass filtered sine wave.
Eight-Bit Ramp Rate Clock—when Shaped On/Off Keying is
engaged, this down-counter takes the system clock (300 MHz
maximum), and divides it by an 8-bit binary value (programmed
by the user) to produce a user-defined clock. The clock outputs
one pulse every time the counter counts down to zero. This clock is
270 DEGREES
90 DEGREES
100 (BPSK)
F1
or CMOS logic
REV. 0