AD9927 Analog Devices, AD9927 Datasheet - Page 75

• Manufacturer Part Number: AD9927
• Description: 14-Bit CCD Signal Processor
• Manufacturer: Analog Devices

Vertical Toggle Position Placement Near Counter Reset
An additional consideration during the reset of the internal
counters is the vertical toggle position placement. Prior to the
internal counters being reset, there is a region of 36 pixels
during which no toggle positions should be programmed.
As shown in Figure 91, for master mode the last 36 pixels before
the HD falling edge must not be used for toggle position placement
of the V, VSG, SUBCK, HBLK, PBLK, or CLPOB pulses.
(PIXEL COUNTER)
PIXEL NO.
CLPOB
H-COUNTER
NOTES
1. EXTERNAL HD FALLING EDGE IS LATCHED BY CLI RISING EDGE, AND THEN LATCHED AGAIN BY SHD INTERNAL FALLING EDGE.
2. INTERNAL H-COUNTER IS ALWAYS RESET 35.5 CLOCK CYCLES AFTER THE INTERNAL HD FALLING EDGE.
3. DEPENDING ON THE VALUE OF SHDLOC, H-COUNTER RESET CAN OCCUR 36 OR 37 CLI CLOCK EDGES AFTER THE EXTERNAL HD FALLING EDGE.
4. SHDLOC = 0 IS SHOWN IN ABOVE EXAMPLE. IN THIS CASE, THE H-COUNTER RESET OCCURS 36 CLI RISING EDGES AFTER HD FALLING EDGE.
5. HD FALLING EDGE SHOULD OCCUR COINCIDENT WITH VD FALLING EDGE (WITHIN SAME CLI CYCLE) OR AFTER VD FALLING EDGE. HD FALLING
INTERNAL
INTERNAL
HD
H1
EDGE SHOULD NOT OCCUR WITHIN FIVE CLI CYCLES PRIOR TO THE VD FALLING EDGE.
SHD
0
CLI
1
2
3
4
VD
HD
HD
HBLKTOG1
HBLKTOG2
CLPOB_TOG1
CLPOB_TOG2
X
X
X
t
VDHD
3ns MIN
X
MASTER MODE
3ns MIN
Figure 90. Example of Slave Mode Register Setting to Obtain Desired Toggle Positions
X X
Figure 89. External VD/HD and Internal H-Counter Synchronization, Slave Mode
60
100
103
112
X
X
X
X
SLAVE MODE
(60 – 36) = 24
(100 – 36) = 64
(103 – 36) = 67
(112 – 36) = 76
X
t
CLIDLY
X
X
X X X
Rev. 0 | Page 75 of 100
X
X
35.5 CYCLES
60
X
1
X X
Figure 92 shows the same example for slave mode. The same
restriction applies: the last 36 pixels before the counters are
reset cannot be used. However, in slave mode, the counter reset
is delayed with respect to VD/HD placement, so the inhibited
area is different than it is in master mode.
It is recommended that Pixel Location 0 not be used for any of
the toggle positions for the VSG and SUBCK pulses.
X
X
X
X
X X X
100
2
3
103
X
X
112
X
4
X
X
X
X
X
X
0
H-COUNTER
RESET
1 2
AD9927