AD9927 Analog Devices, AD9927 Datasheet - Page 84

• Manufacturer Part Number: AD9927
• Description: 14-Bit CCD Signal Processor
• Manufacturer: Analog Devices

AD9927
UPDATING NEW REGISTER VALUES
The AD9927’s internal registers are updated at different times,
depending on the particular register. Table 47 summarizes the
four register update types: SCK, VD, SG-Line, and SCP. Tables
in the Complete Register Listing section also contain an Update
Type column that identifies when each register is updated.
• SCK Updated —As soon as the 28th data bit (D27) is clocked
• VD Updated —More registers are updated at the next VD
• SG-Line Updated —A few of the shutter registers are updated
Table 47. Register Update Locations
Update Type
SCK
VD
SG-Line
SCP
in, some registers are immediately updated. These registers
are used for functions that do not require gating with the next
VD boundary, such as power-up and reset functions.
falling edge. By updating these values at the next VD edge,
the current field is not corrupted and the new register values
are applied to the next field. The VD update can be further
delayed past the VD falling edge by using the UPDATE
register (Address 0x17). This delays the VD-updated register
updates to any HD line in the field. Note that the field
registers are not affected by the UPDATE register.
at the HD falling edge at the start of the SG active line. These
registers control the SUBCK signal so that the SUBCK output
is not updated until the SG line occurs.
XV1 TO XV24
SERIAL
WRITE
VSG
VD
HD
Description
When the 28th data bit (D27) is clocked in, the register is immediately updated.
Register is updated at the VD falling edge. VD-updated registers can be delayed further by using the UPDATE register at
Address 0x17. FIELD registers are not affected by the UPDATE register.
Register is updated at the HD falling edge at the start of the SG-active line.
Register is updated at the next SCP when the register is used.
UPDATED
SCK
Figure 101. Register Update Locations (See Table 47 for Definitions)
SCP0
USE VSEQ2
UPDATED
REGION 0
VD
SCP1
UPDATED
SGLINE
USE VSEQ3
REGION 1
SG
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SCP2
UPDATED
SCP
• SCP Updated —At the next SCP where they are used, the
Caution
It is recommended that the registers in the configurable address
area not be written within 36 pixels of any HD falling edge
where a sequence change position (SCP) occurs. See Figure 91
and Figure 92 for an example of what this inhibit area looks like
in master and slave modes. This restriction applies to the V-
pattern, V-sequence, and field registers. As shown in Figure
101, writing to these registers before the VD falling edge
typically avoids loading these registers during SCP locations.
V-pattern group and V-sequence registers are updated. For
example, in Figure 101 this field has selected Region 1 to use
VSEQ3 for the vertical outputs. This means that a write to
any of the VSEQ3 registers, or any of the V-pattern group
registers, which are referenced by VSEQ3, updates at SCP1. If
multiple writes are done to the same register, the last one
done before SCP1 is the one that is updated. Likewise,
register writes to any VSEQ5 registers are updated at SCP2,
and register writes to any VSEQ8 registers are updated at
SCP3.
USE VSEQ5
REGION 2
SCP3
USE VSEQ8
REGION 3
SCP0