AD9948 Analog Devices, AD9948 Datasheet - Page 18

• Manufacturer Part Number: AD9948
• Description: 10-Bit CCD Signal Processor with Precision Timing Core
• Manufacturer: Analog Devices

AD9948
Register
HBLKDIR
HBLKPOL
HBLKEXTMASK
H-COUNTER SYNCHRONIZATION
The H-Counter reset occurs seven CLI cycles following the HD
falling edge. The PxGA steering is synchronized with the reset
of the internal H-Counter (see Figure 13).
(PIXEL COUNTER)
H-COUNTER
PxGA GAIN
REGISTER
CLI
VD
HD
NOTES
1. INTERNAL H-COUNTER IS RESET SEVEN CLI CYCLES AFTER THE HD FALLING EDGE (WHEN USING VDHDEDGE = 0).
2. TYPICAL TIMING RELATIONSHIP: CLI RISING EDGE COINCIDES WITH HD FALLING EDGE.
3. PxGA STEERING IS SYNCHRONIZED WITH THE RESET OF THE INTERNAL H-COUNTER (MOSAIC SEPARATE MODE IS SHOWN).
X
X
X
X
1b
1b
1b
Length
X
X
SEQUENCE CHANGE OF POSITION 1
SEQUENCE CHANGE OF POSITION 0
SEQUENCE CHANGE OF POSITION 2
SEQUENCE CHANGE OF POSITION 3
X
X
X
X
UP TO FOUR INDIVIDUAL HORIZONTAL CLAMP AND BLANKING REGIONS MAY BE
PROGRAMMED WITHIN A SINGLE FIELD, USING THE SEQUENCE CHANGE POSITIONS.
Figure 12. Clamp and Blanking Sequence Flexibility
X
X
High/Low
Range
High/Low
High/Low
X
X
Table XV. External HBLK Register Parameters
(V-COUNTER = 0)
X
X
Figure 13. H-Counter Synchronization
X
X
H-COUNTER
RESET
X
X
0
0
Description
Specifies HBLK Internally Generated or Externally Supplied.
1 = External.
External HBLK Active Polarity.
0 = Active Low.
1 = Active High.
External HBLK Masking Polarity.
0 = Mask H1 Low.
1 = Mask H1 High.
SINGLE FIELD (1 VD INTERVAL)
1
1
–18–
0
2
CLAMP AND PBLK SEQUENCE REGION 0
CLAMP AND PBLK SEQUENCE REGION 1
CLAMP AND PBLK SEQUENCE REGION 2
CLAMP AND PBLK SEQUENCE REGION 3
1
3
0
4
5
1
0
6
1
7
8
0
9
1
10
0
11
1
12
0
14
1
15
0
0
2
1
3
2
2
REV. 0
3
3