CY3130R62 Cypress Semiconductor Corp., CY3130R62 Datasheet - Page 2

• Manufacturer Part Number: CY3130R62
• Description: Warp Enterprise VHDL PC
• Manufacturer: Cypress Semiconductor Corp.

VHDL Compiler
VHDL is a powerful, industry-standard language for behavioral
design entry and simulation, and is supported by all major ven-
dors of EDA tools. It allows designers to learn a single lan-
guage that is useful for all facets of the design process.
VHDL offers designers the ability to describe designs at many
different levels. At the highest level, designs can be entered
as a description of their behavior. This behavioral description
is not tied to any specific target device. As a result, simulation
can be done very early in the design to verify correct function-
ality, which significantly speeds the design process.
The Warp syntax for VHDL includes support for intermediate
level entry modes such as state tables and Boolean entry. At
the lowest level, designs can be described using gate-level
descriptions. Warp Enterprise gives the designer the flexibility
to intermix all of these entry modes.
In addition, VHDL allows you to design hierarchically, building
up entities in terms of other entities. This feature allows you to
work either “top-down” (designing the highest levels of the sys-
tem and its interfaces first, then progressing to greater and
greater detail) or “bottom-up” (designing elementary building
blocks of the system, then combining these to build larger and
larger parts) with equal ease.
Because this language is an IEEE standard, multiple vendors
offer tools for design entry and simulation at both high and low
levels and synthesis of designs to different silicon targets. The
use of device-independent behavioral design entry gives
users the freedom to easily migrate to high volume technolo-
gies. The wide availability of VHDL tools provides complete
vendor independence as well. Designers can begin their
project using Warp Enterprise for Cypress CPLDs and con-
vert to high-volume ASICs using the same VHDL behavioral
description with industry-standard synthesis tools.
Document #: 38-03050 Rev. *A
VHDL
text
Programming
File
Figure 1. Warp
Source-Level
Simulation
Graphical
HDL Blocks
®
UltraGen™
Synthesis
Simulator
Design Flow
Timing
Fitting
and
State Machine
Simulation Models
VHDL, Verilog
&Third-Party
The VHDL language also allows users to define their own
functions. User-defined functions allow users to extend the
capabilities of the language and build reusable files of tested
routines. VHDL provides control over the timing of events or
processes. It has constructs that identify processes as either
sequential, concurrent, or a combination of both. This feature
is essential when describing the interaction of complex state
machines.
VHDL is a rich programming language. Its flexibility reflects the
nature of modern digital systems and allows designers to cre-
ate accurate models of digital designs. Because it is not a ver-
bose language it is easy to learn and compile. In addition,
models created in VHDL can readily be transported to other
EDA Environments. Warp Enterprise VHDL supports IEEE
1076/1164 VHDL including loops, for/generate statements,
full hierarchical designs with packages, enumerated types,
and integers.
A VHDL Design Example
Design Entry
Warp Enterprise descriptions specify:
The part of a Warp Enterprise description that specifies the
behavior or structure of the design is called an entity/archi-
tecture pair. Entity/architecture pairs, as their name implies,
are divided into two parts: an entity declaration, which de-
clares the design’s interface signals (i.e., defines what ex-
ternal signals the design has, and what their directions and
types are), and a design architecture, which describes the
design’s behavior or structure.
The entity portion of a design file is a declaration of what a
design presents to the outside world (the interface). For each
external signal, the entity declaration specifies a signal name,
a direction and a data type. In addition, the entity declaration
specifies a name by which the entity can be referenced in a
design architecture. This section shows code segments from
five sample design files. The top portion of each example
features the entity declaration.
Behavioral Description
The architecture portion of a design file specifies the function
of the design. As shown in Figure 1, multiple design-entry
methods are supported in Warp Enterprise. A behavioral
description in VHDL often includes well known constructs
such as If...Then...Else, and Case statements. Here is a
code segment from a simple state machine design (soda
vending machine) that uses behavioral VHDL to implement
the design:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY drink IS
std_logic;
std_logic);
END drink;
• The behavior or structure of a design, and
• The mapping of signals in a design to the pins of a
PORT (nickel,dime,quarter,clock:#in
PLD/CPLD (optional)
returnDime,returnNickel,giveDrink:out
CY3130
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