CY3130R62 Cypress Semiconductor Corp., CY3130R62 Datasheet - Page 4

• Manufacturer Part Number: CY3130R62
• Description: Warp Enterprise VHDL PC
• Manufacturer: Cypress Semiconductor Corp.

BEGIN
END mixed;
Boolean Equations
A third design-entry method available to Warp Enterprise users
is Boolean equations. Figure 2 displays a schematic of a simple
one-bit half adder. The following code describes how this one-bit half
adder can be implemented in Warp Enterprise with Boolean equa-
tions:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--entity declaration
ENTITY half_adder IS
END half_adder;
--architecture body
ARCHITECTURE behave OF half_adder IS
BEGIN
END behave;
Structural VHDL
While all of the design methodologies described thus far are
high-level entry methods, structural VHDL provides a method
for designing at a very low level. In structural descriptions, the
designer simply lists the components that make up the design
and specifies how the components are wired together.
Figure 3 displays the schematic of a simple 3-bit shift register and
the following code shows how this design can be described in
Warp Enterprise using structural VHDL:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.rtlpkg.all;
Document #: 38-03050 Rev. *A
”0001”& ”0000110”,
”0010”& ”1011011”,
”0011”& ”1001111”,
”0100”& ”1100110”,
”0101”& ”1101101”,
”0110”& ”1111101”,
”0111”& ”0000111”,
”1000”& ”1111111”,
”1001”& ”1101111”,
”101-”& ”1111100”, --creates E pattern
”111-”& ”1111100”
);
PORT (x, y: IN std_logic;
sum <= x XOR y;
carry <= x AND y;
outputs <= ttf(truthTable,inputs);
sum, carry : OUT std_logic);
y
x
Figure 2. One-Bit Half Adder
sum
carry
ENTITY shifter3 IS port (
ARCHITECTURE struct OF shifter3 IS
All of the design-entry methods described can be mixed as
desired. VHDL has the ability to combine both high- and
low-level entry methods in a single file. The flexibility and
power of VHDL allows users of Warp Enterprise to describe
designs using whatever method is appropriate for their particular
design.
Finite State Machine Editor
Aldec’s Active-HDL FSM finite state machine editor, allows
graphic design entry through the use of graphical state dia-
grams. A design may be represented graphically using state
diagrams and data flow logic. This tool will automatically
generate the HDL code of the design.
HDL Block Diagram Editor
The HDL block diagram editor lets you represent portions of
your code with graphical symbols. This representation allows
you to view the high-level structure of your complex designs
and lets you copy and paste entire modules of your design
within or between designs. The editor comes with a library of
HDL blocks optimized for Cypress devices. Warp Enterprise
comes with a utility that converts HDL text into these blocks.
Language Assistant
The language assistant is a library of language templates that
you can browse and automatically insert into your HDL text.
They provide syntax and structure and give examples to aid
users who are new using a particular HDL.
Flow Manager
The flow manager is a special interface that helps you keep
track of your complex projects. It arranges the tools as part of
1
END shifter3;
SIGNAL q0_temp, q1_temp, q2_temp : STD_LOGIC;
BEGIN
END struct;
Figure 3. Three-Bit Shift Register Circuit Design
clk : IN STD_LOGIC;
x : IN STD_LOGIC;
q0 : OUT STD_LOGIC;
q1 : OUT STD_LOGIC;
q2 : OUT STD_LOGIC);
d1 : DFF PORT MAP(x,clk,q0_temp);
d2 : DFF PORT MAP(q0_temp,clk,q1_temp);
d3 : DFF PORT MAP(q1_temp,clk,q2_temp);
q0 <= q0_temp;
q1 <= q1_temp;
q2 <= q2_temp;
clk
x
d
clk
q
q0
d
clk
q
q1
d
clk
q
CY3130
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q2