MAX108 Maxim, MAX108 Datasheet - Page 18

• Manufacturer Part Number: MAX108
• Description: 5V / 1.5Gsps / 8-Bit ADC with On-Chip 2.2GHz Track/Hold Amplifier
• Manufacturer: Maxim

±5V, 1.5Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
Table 4. Ideal Input Voltage and Output Code Results for Differential Operation
The MAX108 provides a control input (VOSADJ) to com-
pensate for system offsets. The offset adjust input is a
self-biased voltage divider from the internal +2.5V preci-
sion reference. The nominal open-circuit voltage is one-
half the reference voltage. With an input resistance of
typically 25kΩ, this pin may be driven by an external
10kΩ potentiometer (Figure 11) connected between
REFOUT and GNDI to correct for offset errors. This con-
trol provides a typical ±5.5LSB offset adjustment range.
The MAX108 clock inputs are designed for either sin-
gle-ended or differential operation (Figure 12) with flexi-
ble input drive requirements. Each clock input is
terminated with an on-chip, laser-trimmed 50Ω resistor
to CLKCOM (clock-termination return). The CLKCOM
termination voltage can be connected anywhere
between ground and -2V for compatibility with standard
ECL drive levels.
The clock inputs are internally buffered with a preampli-
fier to ensure proper operation of the data converter,
even with small-amplitude sine-wave sources. The
MAX108 was designed for single-ended, low-phase-
noise sine-wave clock signals with as little as 100mV
amplitude (-10dBm). This eliminates the need for an
external ECL clock buffer and its added jitter.
Excellent performance is obtained by AC- or DC-cou-
pling a low-phase-noise sine-wave source into a single
clock input (Figure 13a, Table 5). For proper DC bal-
ance, the undriven clock input should be externally
50Ω reverse-terminated to GNDI.
The dynamic performance of the data converter is
essentially unaffected by clock-drive power levels from
-10dBm (100mV clock signal amplitude) to +10dBm
(1V clock signal amplitude). The MAX108 dynamic per-
18
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+125mV - 0.5LSB
-125mV + 0.5LSB
Single-Ended Clock Inputs (Sine-Wave Drive)
+125mV
-125mV
VIN+
0V
-125mV + 0.5LSB
+125mV - 0.5LSB
Clock Operation
+125mV
-125mV
VIN-
0V
Offset Adjust
OVERRANGE BIT
Figure 11. Offset Adjust with External 10k Ω Potentiometer
Figure 12. Simplified Clock Input Structure (Single-Ended/
Differential)
CLOCK INPUTS ARE
ESD PROTECTED
(NOT SHOWN IN THIS
SIMPLIFIED DRAWING).
1
0
0
0
0
CLKCOM
CLK+
CLK-
GNDI
POT
10k
REFOUT
50
50
VOSADJ
00000000 (zero scale)
11111111 (full scale)
MAX108
OUTPUT CODE
11111111
01111111
10000000
00000001
toggles
GNDI
+0.8V
V
EE