XR16L580 Exar Corporation, XR16L580 Datasheet - Page 32

• Manufacturer Part Number: XR16L580
• Description: Smallest 2.25 to 5.5V Uart With 16-Byte Fifo And Power-save
• Manufacturer: Exar Corporation

XR16L580
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
EFR[4]: Enhanced Function Bits Enable
Enhanced function control bit. This bit enables IER bits 4-7, ISR bits 4-5, FCR bits 4-5, MCR bits 2, 5, 6 and 7
to be modified. After modifying any enhanced bits, EFR bit-4 can be set to a logic 0 to latch the new values.
This feature prevents legacy software from altering or overwriting the enhanced functions once set. Normally, it
is recommended to leave it enabled, logic 1.
EFR[5]: Special Character Detect Enable
Logic 0 = modification disable/latch enhanced features. IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 2, 5-
7 are saved to retain the user settings. After a reset, the IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 2,
5-7 are set to a logic 0 to be compatible with ST16C550 mode (default).
Logic 1 = Enables the above-mentioned register bits to be modified by the user.
Logic 0 = Special Character Detect Disabled (default).
Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with data in
Xoff-2 register. If a match exists, the receive data will be transferred to FIFO and ISR bit-4 will be set to indicate
detection of the special character. Bit-0 corresponds with the LSB bit of the receive character. If flow control is set
for comparing Xon1, Xoff1 (EFR [1:0]= ‘10’) then flow control and special character work normally. However, if flow
control is set for comparing Xon2, Xoff2 (EFR[1:0]= ‘01’) then flow control works normally, but Xoff2 will not go to
the FIFO, and will generate an Xoff interrupt and a special character interrupt, if enabled via IER bit-5.
EFR
C
ONT
X
X
X
0
0
1
0
1
1
0
1
0
BIT
-3
-3
EFR
C
ONT
X
X
X
0
0
0
1
1
0
1
1
0
BIT
-2
-2
T
ABLE
EFR
C
ONT
10: S
X
X
X
X
0
0
1
0
1
1
1
1
BIT
-1
-1
OFTWARE
EFR
C
ONT
0
X
X
X
X
0
0
1
1
1
1
1
F
BIT
32
LOW
-0
-0
C
No TX and RX flow control (default and reset)
No transmit flow control
Transmit Xon1, Xoff1
Transmit Xon2, Xoff2
Transmit Xon1 and Xon2, Xoff1 and Xoff2
No receive flow control
Receiver compares Xon1, Xoff1
Receiver compares Xon2, Xoff2
Transmit Xon1, Xoff1
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
Transmit Xon2, Xoff2
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
Transmit Xon1 and Xon2, Xoff1 and Xoff2,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
No transmit flow control,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
ONTROL
T
RANSMIT AND
F
UNCTIONS
R
ECEIVE
S
OFTWARE
áç
áç
áç
áç
F
LOW
C
REV. 1.2.0
ONTROL