XR17C158 Exar Corporation, XR17C158 Datasheet - Page 18

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XR17C158

Manufacturer Part Number
XR17C158
Description
Eight-channel Pci-based (UART)
Manufacturer
Exar Corporation
Datasheet

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PRELIMINARY
MPIOINT [7:0] (default 0x00)
Enable multipurpose input pin interrupt. If the pin is
selected by MPIOSEL as input then bit-0 enables in-
put pin 0 for interrupt, and bit-7 enables input pin 7.
No interrupt is enable if the pin is selected to be an
output. The interrupt is edge sensing and determined
by MPIOINV and MPIOLVL registers. The MPIO in-
terrupt clears after a read to register MPIOLVL. The
combination of MPIOLVL and MPIOINV determines
the interrupt being active low or active high, it’s level
trigger. Logic 0 (default) disables the pin’s interrupt
and logic 1 enables it.
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
MPIO7
Multipurpose Input/Output Interrupt Enable
MPIO6
MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0
MPIOINT Register
F
IGURE
MPIOINT [7:0]
MPIOLVL [7:0]
Read Input Level
MPIOINV [7:0]
(Input Inversion Enable =1)
MPIOLVL [7:0]
(Output Level)
MPIO3T [7:0]
(3-state Enable =1)
MPIOSEL [7:0]
(Select Input=1, Output=0 )
INT
6. M
ULTIPURPOSE INPUT
AND
Rising Edge
Detection
OR
/
OUTPUT INTERNAL CIRCUIT
1
0
18
MPIOLVL [7:0] (default 0x00)
Output pin level control and input level status. The
status of the input pin(s) is read on this register and
output pins are controlled on this register. A logic 0
(default) sets the output to low and a logic 1 sets the
output pin to high. The MPIO interrupt will clear upon
reading this register.
MPIO3T [7:0] (default 0x00)
Output pin tri-state control. A logic 0 (default) sets
the output to active level per register MPIOBIT set-
tling, a logic 1 sets the output pin to tri-state.
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
MPIO7
AND
PCI BUS OCTAL UART
MPIO6
Multipurpose Output Level Control
MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0
MPIOLVL Register
Pin [7:0]
MPIO
MPIOCKT
XR17C158
REV. 1.0.0

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