AT90CAN128-16AE ATMEL Corporation, AT90CAN128-16AE Datasheet - Page 270

• Manufacturer Part Number: AT90CAN128-16AE
• Description: 8-bit Avr Microcontroller With 128K Bytes of Isp Flash And CAN Controller.flash (Kbytes) 128 Vcc (V) 2.7-5.5 EEPROM (Kbytes) 4 SRAM (bytes) 4K CAN (mess. Obj.) 15
• Manufacturer: ATMEL Corporation

ADC Input Channels
ADC Voltage Reference
ADC Noise Canceler
270
AT90CAN128
When changing channel selections, the user should observe the following guidelines to
ensure that the correct channel is selected:
•
•
When switching to a differential gain channel, the first conversion result may have a
poor accuracy due to the required settling time for the automatic offset cancellation cir-
cuitry. The user should preferably disregard the first conversion result.
The reference voltage for the ADC (V
Single ended channels that exceed V
selected as either AV
AV
generated from the internal bandgap reference (V
either case, the external AREF pin is directly connected to the ADC, and the reference
voltage can be made more immune to noise by connecting a capacitor between the
AREF pin and ground. V
voltmeter. Note that V
be connected in a system.
If the user has a fixed voltage source connected to the AREF pin, the user may not use
the other reference voltage options in the application, as they will be shorted to the
external voltage. If no external voltage is applied to the AREF pin, the user may switch
between AV
switching reference voltage source may be inaccurate, and the user is advised to dis-
card this result.
If differential channels are used, the selected reference should not be closer to AV
than indicated in Table 139 on page 361.
The ADC features a noise canceler that enables conversion during sleep mode to
reduce noise induced from the CPU core and other I/O peripherals. The noise canceler
can be used with ADC Noise Reduction and Idle mode. To make use of this feature, the
following procedure should be used:
CC
In Single Conversion mode, always select the channel before starting the
conversion. The channel selection may be changed one ADC clock cycle after
writing one to ADSC. However, the simplest method is to wait for the conversion to
complete before changing the channel selection.
In Free Running mode, always select the channel before starting the first
conversion. The channel selection may be changed one ADC clock cycle after
writing one to ADSC. However, the simplest method is to wait for the first conversion
to complete, and then change the channel selection. Since the next conversion has
already started automatically, the next result will reflect the previous channel
selection. Subsequent conversions will reflect the new channel selection.
1. Make sure that the ADC is enabled and is not busy converting. Single Con-
2. Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a con-
3. If no other interrupts occur before the ADC conversion completes, the ADC
is connected to the ADC through a passive switch. The internal 2.56V reference is
version mode must be selected and the ADC conversion complete interrupt
must be enabled.
version once the CPU has been halted.
interrupt will wake up the CPU and execute the ADC Conversion Complete
interrupt routine. If another interrupt wakes up the CPU before the ADC con-
version is complete, that interrupt will be executed, and an ADC Conversion
Complete interrupt request will be generated when the ADC conversion
CC
and 2.56V as reference selection. The first ADC conversion result after
CC
REF
, internal 2.56V reference, or external AREF pin.
REF
is a high impedant source, and only a capacitive load should
can also be measured at the AREF pin with a high impedant
REF
REF
will result in codes close to 0x3FF. V
) indicates the conversion range for the ADC.
BG
) through an internal amplifier. In
4250C–CAN–03/04
REF
can be
CC