DM336P Davicom Semiconductor Incorporated, DM336P Datasheet - Page 25

• Manufacturer Part Number: DM336P
• Manufacturer: Davicom Semiconductor Incorporated

DM6381/82 Pin Description (continued)
Final
Version: DM336P-DS-F02
August 15, 2000
Pin No.
91 - 92
100
96
97
98
99
69
73
74
75
76
TEST, TEST1
Pin Name
RD_SP1
FR_SP1
TD_SP1
TD_SP2
/RESET
/IRQ0
/IRQ1
/IRQ2
/IRQ3
SCLK
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
I/O
I/O
O
O
I
I
I
I
I
I
I
I
Reset Pin Of DSP Chip, low active.
Interrupt 0 Input
Interrupt 1 Input
Interrupt 2 Input
Interrupt 3 Input
These three pins define the testing mode operation of
DM6381/DM6382 as followed:
When Test=0
Test1
When Test=1:
Reserved for mass production testing mode.
All these 2 pins are pulled low internally.
Frame Signal Of Serial Port 1
Data Output Pin Of Serial Port 1
The serial data is clocked out through this pin according to the rising
edge of SCLK. The MSB is sent immediately after the falling edge of the
FR_SP1 signal.
Data Input Pin Of The Serial Port 1
The serial data is sampled at the falling edge of the SCLK. The MSB is
coming immediately after the falling of FR_SP1 signal.
Reference Clock For Serial Port 1 And Serial Port 2
Data Output Pin Of Serial Port 2
The serial data is clocked out through this pin according to the rising
edge of SCLK. The MSB is sent immediately after the falling edge of the
FR_SP2 signal.
0, PLL output clock is 89.74MHz.
1, PLL output clock is 80.64MHz.
Description
DM336P
25