DM336P Davicom Semiconductor Incorporated, DM336P Datasheet - Page 26

• Manufacturer Part Number: DM336P
• Manufacturer: Davicom Semiconductor Incorporated

DM6381/82 Functional Description
1. System Clock
a. Reference Oscillator Clock
The reference oscillator is provided by an external
40.32 MHz crystal, this is the clock source of the Data
Pump chipset.
b. DSP Clock
This DSP clock is the output of the PLL frequency
synthesizer and its frequency can be selected by
Test1 pin. (see pin description )
c. CODEC Clock
This clock is output via the CODEC_CLK Pin as the
reference clock of the codec chip. This clock is
derived from dividing reference oscillator clock by
two.
d. MSCLK Clock
This clock is derived from dividing the DSP clock by 2
or 4, the divider is programmed by DIV bit
(configuration register bit 14 ) as followed:
DM6381/82 Absolute Maximum Ratings*
Power supply voltage ......................... -0.5V to +7.0V
Case operating temperature.................. 0
Storage temperature ........................ -65
Applied voltage on any pin .......................................
26
.......................................... -0.5V
Config Reg bit 14
0
1
Divider
2
4
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
VIN
o
C to 150
o
VDD+0.5V
C to 85
o
o
C
C
2. Serial Port
There are two serial ports to provide the interface with
CODEC chip. The serial port 1 (SP1) transfer 32 bits
in each frame while the serial port 2 can transfer 64
bits in each frame. The frame signal of each serial
port can be configured as either input signal or output
signal by the Serial Port Control Register (SPC).
3. Dual Port RAM
The 16 X 8 dual port RAM allows easy system
expansion by adding another DSP or micro-processor.
Address 2000h ~ 200Fh are reserved for this dual
port RAM. The 8 bits dual port RAM data correspond
to the MSBs of the data bus (bit 15 ~ bit 8) of the DSP
core. Upon reading the dual port RAM, the 8 lsb
contents (bit 7 to bit 0) are all 0. For the convenience
of description, the micro-controller port is referred to
as B port and the DSP port is referred to as A port.
4. Interrupt
The DSP core provides 4 nested interrupt inputs:
IRQ3, IRQ2, IRQ1, IRQ0. IRQ3 is the highest priority
input and IRQ0, the lowest. In the V.34 and V.32
application, the IRQ3, IRQ2 and IRQ1 are defined as
external interrupt triggered from the pin IRQ3B,
IRQ2B, IRQ1B respectively.
Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to
this device. These are stress ratings only. Functional
operation of this device at these or any other
conditions above those indicated in the operational
sections of this specification is not implied or
intended. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
*Comments
Version: DM336P-DS-F02
DM336P
August 15, 2000
Final