LPC2119 Philips Semiconductors (Acquired by NXP), LPC2119 Datasheet - Page 22

• Manufacturer Part Number: LPC2119
• Description: Single-chip 16/32-bit Microcontrollers; 128/256 KB Isp/iap Flash With 10-bit ADC And CANthe LPC2119/LPC2129 Are Based on a 16/32 Bit ARM7TDMI-STM Cpu With Real-time Emulation And Embedded Trace Support, Together With 128/256 Kilobytes (kB) of Embedde
• Manufacturer: Philips Semiconductors (Acquired by NXP)

Philips Semiconductors
9397 750 12806
Preliminary data
6.20.4 External interrupt inputs
6.20.5 Memory Mapping Control
6.20.6 Power Control
6.20.7 VPB bus
The Wake-up Timer monitors the crystal oscillator as the means of checking whether
it is safe to begin code execution. When power is applied to the chip, or some event
caused the chip to exit Power-down mode, some time is required for the oscillator to
produce a signal of sufficient amplitude to drive the clock logic. The amount of time
depends on many factors, including the rate of V
the type of crystal and its electrical characteristics (if a quartz crystal is used), as well
as any other external circuitry (e.g. capacitors), and the characteristics of the
oscillator itself under the existing ambient conditions.
The LPC2119/LPC2129 include up to nine edge or level sensitive External Interrupt
Inputs as selectable pin functions. When the pins are combined, external events can
be processed as four independent interrupt signals. The External Interrupt Inputs can
optionally be used to wake up the processor from Power-down mode.
The Memory Mapping Control alters the mapping of the interrupt vectors that appear
beginning at address 0x00000000. Vectors may be mapped to the bottom of the
on-chip Flash memory, or to the on-chip static RAM. This allows code running in
different memory spaces to have control of the interrupts.
The LPC2119/LPC2129 support two reduced power modes: Idle mode and
Power-down mode. In Idle mode, execution of instructions is suspended until either a
Reset or interrupt occurs. Peripheral functions continue operation during Idle mode
and may generate interrupts to cause the processor to resume execution. Idle mode
eliminates power used by the processor itself, memory systems and related
controllers, and internal buses.
In Power-down mode, the oscillator is shut down and the chip receives no internal
clocks. The processor state and registers, peripheral registers, and internal SRAM
values are preserved throughout Power-down mode and the logic levels of chip
output pins remain static. The Power-down mode can be terminated and normal
operation resumed by either a Reset or certain specific interrupts that are able to
function without clocks. Since all dynamic operation of the chip is suspended,
Power-down mode reduces chip power consumption to nearly zero.
A Power Control for Peripherals feature allows individual peripherals to be turned off if
they are not needed in the application, resulting in additional power savings.
The VPB Divider determines the relationship between the processor clock (cclk) and
the clock used by peripheral devices (PCLK). The VPB Divider serves two purposes.
The first is that the VPB bus cannot operate at the highest speeds of the CPU. In
order to compensate for this, the VPB bus may be slowed down to one half or one
fourth of the processor clock rate. The default condition at reset is for the VPB bus to
run at one quarter of the CPU clock. The second purpose of the VPB Divider is to
allow power savings when an application does not require any peripherals to run at
the full processor rate. Because the VPB Divider is connected to the PLL output, the
PLL remains active (if it was running) during Idle mode.
Rev. 02 — 02 February 2004
Single-chip 16/32-bit microcontrollers
LPC2119/LPC2129
DD
ramp (in the case of power on),
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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