LPC2131 Philips Semiconductors (Acquired by NXP), LPC2131 Datasheet - Page 22

• Manufacturer Part Number: LPC2131
• Manufacturer: Philips Semiconductors (Acquired by NXP)

Philips Semiconductors
9397 750 14008
Preliminary data sheet
6.21.1 Crystal oscillator
6.21.2 PLL
6.21.3 Reset and wake-up timer
6.21 System control
The oscillator supports crystals in the range of 10 MHz to 25 MHz. The oscillator output
frequency is called f
purposes of rate equations, etc. f
running and connected. Refer to
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input
frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current Controlled
Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the
multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper
frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so
there is an additional divider in the loop to keep the CCO within its frequency range while
the PLL is providing the desired output frequency. The output divider may be set to divide
by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2,
it is insured that the PLL output has a 50 % duty cycle.The PLL is turned off and bypassed
following a chip reset and may be enabled by software. The program must configure and
activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source. The
PLL settling time is 100 s.
Reset has two sources on the LPC2131/2132/2138: the RESET pin and watchdog reset.
The RESET pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of
chip reset by any source starts the wake-up timer (see wake-up timer description below),
causing the internal chip reset to remain asserted until the external reset is de-asserted,
the oscillator is running, a fixed number of clocks have passed, and the on-chip Flash
controller has completed its initialization.
When the internal reset is removed, the processor begins executing at address 0, which is
the reset vector. At that point, all of the processor and peripheral registers have been
initialized to predetermined values.
The wake-up timer ensures that the oscillator and other analog functions required for chip
operation are fully functional before the processor is allowed to execute instructions. This
is important at power on, all types of reset, and whenever any of the aforementioned
functions are turned off for any reason. Since the oscillator and other functions are turned
off during Power-down mode, any wake-up of the processor from Power-down mode
makes use of the wake-up timer.
The wake-up timer monitors the crystal oscillator as the means of checking whether it is
safe to begin code execution. When power is applied to the chip, or some event caused
the chip to exit Power-down mode, some time is required for the oscillator to produce a
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Match register updates are synchronized with pulse outputs to prevent generation of
erroneous pulses. Software must ‘release’ new match values before they can become
effective.
May be used as a standard timer if the PWM mode is not enabled.
A 32-bit Timer/Counter with a programmable 32-bit Prescaler.
osc
Rev. 01 — 18 November 2004
and the ARM processor clock frequency is referred to as CCLK for
Section 6.21.2 “PLL”
osc
and CCLK are the same value unless the PLL is
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
for additional information.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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