LPC2131 Philips Semiconductors (Acquired by NXP), LPC2131 Datasheet - Page 24

• Manufacturer Part Number: LPC2131
• Manufacturer: Philips Semiconductors (Acquired by NXP)

Philips Semiconductors
9397 750 14008
Preliminary data sheet
6.21.9 VPB bus
6.22.1 EmbeddedICE
6.22 Emulation and debugging
In Power-down mode, the oscillator is shut down and the chip receives no internal clocks.
The processor state and registers, peripheral registers, and internal SRAM values are
preserved throughout Power-down mode and the logic levels of chip output pins remain
static. The Power-down mode can be terminated and normal operation resumed by either
a reset or certain specific interrupts that are able to function without clocks. Since all
dynamic operation of the chip is suspended, Power-down mode reduces chip power
consumption to nearly zero.
A Power Control for Peripherals feature allows individual peripherals to be turned off if
they are not needed in the application, resulting in additional power savings.
The VPB divider determines the relationship between the processor clock (CCLK) and the
clock used by peripheral devices (PCLK). The VPB divider serves two purposes. The first
is to provide peripherals with the desired PCLK via VPB bus so that they can operate at
the speed chosen for the ARM processor. In order to achieve this, the VPB bus may be
slowed down to
properly at power-up (and its timing cannot be altered if it does not work since the VPB
divider control registers reside on the VPB bus), the default condition at reset is for the
VPB bus to run at
is to allow power savings when an application does not require any peripherals to run at
the full processor rate. Because the VPB divider is connected to the PLL output, the PLL
remains active (if it was running) during Idle mode.
The LPC2131/2132/2138 support emulation and debugging via a JTAG serial port. A trace
port allows tracing program execution. Debugging and trace functions are multiplexed only
with GPIOs on Port 1. This means that all communication, timer and interface peripherals
residing on Port 0 are available during the development and debugging phase as they are
when the application is run in the embedded system itself.
Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of
the target system requires a host computer running the debugger software and an
EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts the Remote
Debug Protocol commands to the JTAG data needed to access the ARM core.
The ARM core has a Debug Communication Channel function built-in. The debug
communication channel allows a program running on the target to communicate with the
host debugger or another separate host without stopping the program flow or even
entering the debug state. The debug communication channel is accessed as a
co-processor 14 by the program running on the ARM7TDMI-S core. The debug
communication channel allows the JTAG port to be used for sending and receiving data
without affecting the normal program flow. The debug communication channel data and
control registers are mapped in to addresses in the EmbeddedICE logic.
1
2
1
to
4
Rev. 01 — 18 November 2004
of the processor clock rate. The second purpose of the VPB divider
1
4
of the processor clock rate. Because the VPB bus must work
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
24 of 36