HY29F080 Hynix Semiconductor, HY29F080 Datasheet - Page 12

• Manufacturer Part Number: HY29F080
• Description: 8 Megabit (1M X 8), 5 Volt-only, Flash Memory
• Manufacturer: Hynix Semiconductor

HY29F080
verifies the programmed cell margin. The host is
not required to provide further controls or timings
during this operation. When the Automatic Pro-
gramming algorithm is complete, the device re-
turns to the Read mode. Several methods are
provided to allow the host to determine the status
of the programming operation, as described in the
Write Operation Status section.
Commands written to the device during execution
of the Automatic Programming algorithm are ig-
nored. Note that a hardware reset immediately
terminates the programming operation. To en-
sure data integrity, the aborted program command
sequence should be reinitiated once the reset
operation is complete.
Programming is allowed in any sequence. Only
erase operations can convert a stored “0” to a “1”.
Thus, a bit cannot be programmed from a “0” back
to a “1”. Attempting to do so will set DQ[5] to “1”,
and the Data# Polling algorithm will indicate that
the operation was not successful. A Read/Reset
command or a hardware reset is required to exit
this state, and a succeeding read will show that
the data is still “0”.
Figure 4 illustrates the procedure for the Program
operation.
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N O
Figure 4. Programming Procedure
(See Write Operation Status
Check Programming Status
program Address/Data
C o m m a n d S e q u e n c e :
Last cycle contains
I s s u e P R O G R A M
PROGRAMMING
Last Byte Done?
C O M P L E T E
Section)
START
Y E S
Normal Exit
DQ[5] Error Exit
ERROR RECOVERY
GO TO
Chip Erase Command
The Chip Erase command sequence consists of
two unlock cycles, followed by the erase com-
mand, two additional unlock cycles and then the
chip erase data cycle. During chip erase, all sec-
tors of the device are erased except protected
sector groups. The command sequence starts the
Automatic Erase algorithm, which preprograms
and verifies the entire memory, except for pro-
tected sector groups, for an all zero data pattern
prior to electrical erase. The device then provides
the required number of internally generated erase
pulses and verifies cell erasure within the proper
cell margins. The host system is not required to
provide any controls or timings during these op-
erations.
Commands written to the device during execution
of the Automatic Erase algorithm are ignored. Note
that a hardware reset immediately terminates the
erase operation. To ensure data integrity, the
aborted chip erase command sequence should be
reissued once the reset operation is complete.
When the Automatic Erase algorithm is finished,
the device returns to the Read mode. Several
methods are provided to allow the host to deter-
mine the status of the erase operation, as de-
scribed in the Write Operation Status section.
Figure 5 illustrates the Chip Erase procedure.
Sector Erase Command
The Sector Erase command sequence consists
of two unlock cycles, followed by the erase com-
mand, two additional unlock cycles and then the
sector erase data cycle, which specifies which
(See Write Operation Status
CHIP ERASE COMPLETE
C o m m a n d S e q u e n c e
Issue CHIP ERASE
Check Erase Status
Figure 5. Chip Erase Procedure
Section)
START
Normal Exit
DQ[5] Error Exit
ERROR RECOVERY
GO TO
Rev. 6.1/May 01