HY29F400 Hynix Semiconductor, HY29F400 Datasheet - Page 18

• Manufacturer Part Number: HY29F400
• Description: 4 Megabit (512Kx8/256Kx16) 5 Volt-only Flash Memory
• Manufacturer: Hynix Semiconductor

HY29F400
sector erase timer does not apply to the Chip Erase
command.
After the initial Sector Erase command sequence
is issued, the system should read the status on
DQ[7] (Data# Polling) or DQ[6] (Toggle Bit I) to
ensure that the device has accepted the command
sequence, and then read DQ[3]. If DQ[3] is a ‘1’,
the internally controlled erase cycle has begun and
all further sector erase data cycles or commands
HARDWARE DATA PROTECTION
The HY29F400 provides several methods of pro-
tection to prevent accidental erasure or program-
ming which might otherwise be caused by spuri-
ous system level signals during V
power-down transitions, or from system noise.
These methods are described in the sections that
follow.
Command Sequences
Commands that may alter array data require a
sequence of cycles as described in Table 5. This
provides data protection against inadvertent writes.
18
(Note 4)
Notes:
1. During programming, the program address.
2. Recheck DQ[6] since toggling may stop at the same time as DQ[5] changes from 0 to 1.
3. Use this path if testing for Program/Erase status.
4. Use this path to test whether sector is in Erase Suspend mode.
N O
During sector erase, an address within any sector scheduled for erasure.
at Valid Address (Note 1)
at Valid Address (Note 1)
PROGRAM/ERASE
(Note 3)
DQ[6] Toggled?
Read DQ[7:0]
Read DQ[7:0]
C O M P L E T E
N O
START
Y E S
Figure 8. Toggle Bit I and II Test Algorithm
CC
N O
N O
EXCEEDED TIME ERROR
power-up and
at Valid Address (Note 1)
PROGRAM/ERASE
DQ[6] Toggled?
Read DQ[7:0]
DQ[5] = 1?
(Note 2)
Y E S
Y E S
(other than Erase Suspend) are ignored until the
erase operation is complete. If DQ[3] is a ‘0’, the
device will accept a sector erase data cycle to mark
an additional sector for erasure. To ensure that
the data cycles have been accepted, the system
software should check the status of DQ[3] prior to
and following each subsequent sector erase data
cycle. If DQ[3] is high on the second status check,
the last data cycle might not have been accepted.
Low V
To protect data during V
down, the device does not accept write cycles
when V
command register and all internal program/erase
circuits are disabled, and the device resets to the
Read mode. Writes are ignored until V
than V
signals to the control pins to prevent unintentional
writes when V
IS IN ERASE SUSPEND
SECTOR BEING READ
CC
LKO
CC
DQ[2] Toggled?
Read DQ[7:0]
Read DQ[7:0]
Write Inhibit
is less than V
. The system must provide the proper
Y E S
CC
is greater than V
N O
LKO
CC
(typically 3.7 volts). The
IS NOT IN ERASE SUSPEND
power-up and power-
SECTOR BEING READ
LKO
.
Rev. 5.2/May 01
CC
is greater