ADC10040CIMT National Semiconductor Corporation, ADC10040CIMT Datasheet - Page 16

• Manufacturer Part Number: ADC10040CIMT
• Description: ADC10040 - 10-Bit, 40 Msps, 3V, 55.5 MW A/D Converter, Package: Tssop, Pin Nb=28
• Manufacturer: National Semiconductor Corporation

www.national.com
Functional Description
The ADC10040 uses a pipeline architecture and has error
correction circuitry to help ensure maximum performance.
Differential analog input signals are digitized to 10 bits. Each
analog input signal should have a peak-to-peak voltage
equal to 2.0V, 1.5V or 1.0V, depending on the state of the
IRS pin (pin 5), be centered around V
phase with each other.
Applications Information
1.0 ANALOG INPUTS
The ADC10040 has two analog signal inputs, V
These two pins form a differential input pair. There is one
common mode pin V
mode input voltage.
1.1 REFERENCE PINS
The ADC10040 is designed to operate with a 1.2V reference,
but performs well with reference voltages in the range of
0.8V to 2.0V. Lower reference voltages will decrease the
signal-to-noise ratio (SNR) of the ADC10040. It is very im-
portant that all grounds associated with the reference volt-
age and the input signal make connection to the analog
ground plane at a single point to minimize the effects of
noise currents in the ground path. The three Reference
Bypass Pins V
bypass purposes only. These pins should each be bypassed
to ground with a 0.1 µF capacitor. DO NOT LOAD these pins.
1.2 SIGNAL INPUTS
The signal inputs are V
tude is defined as V
cally in Figure 3:
A single ended input signal is shown in Figure 4.
FIGURE 3. Input Voltage Waveforms for a 2V
FIGURE 4. Input Voltage Waveform for a 2V
REF
, V
IN
CM
REFT
+ − V
IN
Ended Input
that may be used to set the common
+ and V
and V
IN
− and is represented schemati-
REFB
IN
−. The input signal ampli-
, are made available for
CM
/2 and be 180˚ out of
20077848
20077847
IN
P-P
+ and V
P-P
Single
Input
IN
−.
16
The internal switching action at the analog inputs causes
energy to be output from the input pins. As the driving source
tries to compensate for this, it adds noise to the signal. To
prevent this, use 18Ω series resistors at each of the signal
inputs with a 10 pF capacitor across the inputs, as can be
seen in Figure 5. These components should be placed close
to the ADC because the input pins of the ADC is the most
sensitive part of the system and this is the last opportunity to
filter the input. The 10 pF capacitor value is for undersam-
pling application and should be replaced with a 68 pF ca-
pacitor for Nyquist application.
1.3 CLK PIN
The CLK signal controls the timing of the sampling process.
Drive the clock input with a stable, low jitter clock signal in
the range of 10 MHz to 40 MHz with rise and fall times of less
than 2 ns. The trace carrying the clock signal should be as
short as possible and should not cross any other signal line,
analog or digital, not even at 90˚. The CLK signal also drives
an internal state machine. If the CLK is interrupted, or its
frequency is too low, the charge on internal capacitors can
dissipate to the point where the accuracy of the output data
will degrade. This is what limits the lowest sample rate to
10 MSPS. The duty cycle of the clock signal can affect the
performance of any A/D Converter. Because achieving a
precise duty cycle is difficult, the ADC10040 is designed to
maintain performance over a range of duty cycles. While it is
specified and performance is guaranteed with a 50% clock
duty cycle, performance is typically maintained over a clock
duty cycle range of 40% to 60%.
1.4 STBY PIN
The STBY pin, when high, holds the ADC10040 in a power-
down mode to conserve power when the converter is not
being used. The power consumption in this state is 13.5 mW.
The output data pins are undefined in this mode. Power
consumption during power-down is not affected by the clock
frequency, or by whether there is a clock signal present. The
data in the pipeline is corrupted while in the power down.
1.5 DF PIN
The DF pin, when high, forces the ADC10040 to output the
2’s complement data format. When DF is tied low, the output
format is offset binary.
1.6 IRS PIN
The IRS (Input Range Select) pin defines the input signal
amplitude that will produce a full scale output. The table
below describes the function of the IRS pin.
1.7 OUTPUT PINS
The ADC10040 has 10 TTL/CMOS compatible Data Output
pins. The offset binary data is present at these outputs while
the DF and STBY pins are low. While the t
information about output timing, a simple way to capture a
valid output is to latch the data on the rising edge of the
conversion clock. Be very careful when driving a high ca-
pacitance bus. The more capacitance the output drivers
IRS Pin
Floating
V
V
DDA
SSA
TABLE 1. IRS Pin Functions
Full-Scale Input
2.0V
1.5V
1.0V
P-P
P-P
P-P
OD
time provides