ADC10040CIMT National Semiconductor Corporation, ADC10040CIMT Datasheet - Page 7

• Manufacturer Part Number: ADC10040CIMT
• Description: ADC10040 - 10-Bit, 40 Msps, 3V, 55.5 MW A/D Converter, Package: Tssop, Pin Nb=28
• Manufacturer: National Semiconductor Corporation

Symbol
CLK, DF, STBY, SENSE
f
f
t
t
t
t
t
t
t
CLK
CLK
CH
CL
CONV
OD
AD
AJ
STBY
AC Electrical Characteristics
Unless otherwise specified, the following specifications apply for V
2 V
ply for T
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND = V
Note 3: When the voltage at any pin exceeds the power supplies (V
The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two.
Note 4: The absolute maximum junction temperature (T
junction-to-ambient thermal resistance (θ
TSSOP, θ
this device under normal operation will typically be about 55.5 mW. The values for maximum power dissipation listed above will be reached only when the ADC10040
is operated in a severe fault condition.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω.
Note 6: The 235˚C reflow temperature refers to infrared reflow. For Vapor Phase Reflow (VPR) the following conditions apply: Maintain the temperature at the top
of the package body above 183˚C for a minimum of 60 seconds. The temperature measured on the package body must not exceed 220˚C. Only one excursion above
183˚C is allowed per reflow cycle. The analog inputs are protected as shown below. Input voltage magnitude up to 500 mV beyond the supply rails will not damage
this device. However, input errors will be generated if the input goes above V
Note 7: To guarantee accuracy, it is required that |V
Note 8: With the test condition for 2 V
Note 9: Typical figures are at T
Level).
Note 10: Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive and negative
full-scale.
Note 11: Timing specifications are tested at TTL logic levels, V
Note 12: Optimum dynamic performance will be obtained by keeping the reference input in the +1.2V.
Note 13: V
voltage, V
output driver supply voltage, C
Note 14: Power consumption includes output driver power. (f
Note 15: The input bandwidth is limited using a 10 pF capacitor between V
1
2
P-P
, STBY = 0V, V
JA
DR
A
DDIO
Maximum Clock Frequency
Minimum Clock Frequency
Clock High Time
Clock Low Time
Conversion Latency
Data Output Delay after a Rising
Clock Edge
Aperture Delay
Aperture Jitter
Standby Mode Exit Cycle
is 96˚C/W, so P
, and the rate at which the outputs are switching (which is signal dependent). I
= T
is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins, the supply
MIN
to T
Parameter
REF
D
MAX
MAX = 1,302 mW at 25˚C and 677 mW at the maximum operating ambient temperature of 85˚C. Note that the power dissipation of
n
A
is the total load capacitance on the output pin, and f
= T
= 1.20V, (Externally Supplied) f
: all other limits T
J
= 25˚C and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing Quality
P-P
JA
), and the ambient temperature (T
differential input, the 10-bit LSB is 1.95 mV.
DDA
A
–V
J
= 25˚C
max) for this device is 150˚C. The maximum allowable power dissipation is dictated by T
DDIO
SSA
T = 25˚C
IN
IL
| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.
= 0 MHz).
= V
= 0.4V for a falling edge, and V
SSIO
IN
Conditions
<
CLK
= 0V, unless otherwise specified.
V
SSA
IN −
A
), and can be calculated using the formula P
DDA
= 40 MHz, 50% Duty Cycle, C
or V
and V
7
or V
IN
SSA
n
IN +
DDIO
>
is the average frequency at which the pin is toggling.
.
V
= V
DDA
DR
and below V
= V
, V
SSIO
DDIO
IH
DR
(Note 11)
= 2.4V for a rising edge.
20077807
= 0V, V
x (C
Min
or V
2
1
SSA
0
DR
x f
or V
), the current at that pin should be limited to 25 mA.
0
DDA
+ C
SSIO
1
= +3.0V, V
x f
.
L
(Note
1
= 10 pF/pin. Boldface limits ap-
12.5
12.5
Typ
11)
3.3
10
20
+ C
1
2
D
MAX = (T
2
+ f
2
DDIO
+....C
J
max − T
(Note
Max
11)
11
40
= +2.5V, V
6
5
6
x f
11
A
)/θ
) where V
JA
www.national.com
. In the 28-pin
MHz (min)
ps (RMS)
IN
Cycles
Cycles
J
Units
MHz
max, the
DR
ns
ns
ns
ns
ns
=
is the