MCIMX25 Motorola Semiconductor Products, MCIMX25 Datasheet - Page 48

• Manufacturer Part Number: MCIMX25
• Manufacturer: Motorola Semiconductor Products

Timing parameters for UDMA in-burst are listed in
1
Make t
3.6.2.4
Figure 18
48
Parameter
There is a special timing requirement in the ATA host that requires the internal DIOW to go only high three clocks after the last
active edge on the DSTROBE signal. The equation given on this line tries to capture this constraint.
tdzfs
ATA
tenv
tzah
tack
tcyc
tcvh
tmli
tds
tdh
trp
on
—
—
and t
shows the timing for start of UDMA out-transfer.
off
UDMA Out-Transfer Timing
big enough to avoid bus contention.
Parameter
Spec.
tmli1
tdzfs
tenv
tds1
tdh1
tzah
tack
tx1
tcvh
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 2
tc1
ton
toff
trp
1
buffer_en
DMACK
DATA WRITE
DMARQ
tack(min.) = (time_ack
tenv(min.) = (time_env
tenv(max.) = (time_env
tds – (tskew3) – ti_ds > 0
tdh – (tskew3) –ti_dh > 0
(tcyc – tskew) > T
trp(min.) = time_rp
(time_rp
tmli1(min.) = (time_mlix + 0.4)
tzah(min.) = (time_zah + 0.4)
tdzfs = (time_dzfs
tcvh = (time_cvh
ton = time_on
toff = time_off
DIOW
DIOR
IORDY
ADDR
Table 35. Timing Parameters for UDMA In-Burst
Figure 18. Timing for UDMA Out-Transfer Start
T) – (tco + tsu + 3T + 2
tack
T – tskew1
T – tskew1
T) – (tskew1 + tskew2)
T) – (tskew1 + tskew2)
ton
T – (tskew1 + tskew2 + tskew6)
tenv
T) – (tskew1 + tskew2)
T) – (tskew1 + tskew2)
T) + (tskew1 + tskew2)
tdzfs tdvs tdvh tdvs
Table
T
Value
T
tli1
tbuf + 2
35.
tcyc
tcable2) > trfs (drive)
tcyc
trfs1
Freescale Semiconductor
Required Conditions
should be low enough
tskew3, ti_ds, ti_dh
T big enough
time_mlix
time_dzfs
time_ack
time_env
time_zah
time_cvh
time_rp
time_rp
—