AD1816 Analog Devices, AD1816 Datasheet - Page 31

• Manufacturer Part Number: AD1816
• Description: Single Chip Plug And Play Multimedia Audio Subsystem
• Manufacturer: Analog Devices

REV. A
LBTD [7:0] Low Byte Temporary Data holding latch for register pair writes;
XC0
XC1
TE
SIE
JIE
ADDRESS
00 (0x00)
13 (0x0D)
32 (0x20)
35 (0x23)
36 (0x24)
41 (0x29 )
45 (0x2D)
[00] INDIRECT LOW BYTE TMP
10 (0x0A)
11 (0x0B)
12 (0x0C)
14 (0x0E)
15 (0x0F)
42 (0x2A)
43 (0x2B)
44 (0x2C)
46 (0x2E)
01 (0x01)
02 (0x02)
03 (0x03)
04 (0x04)
05 (0x05)
06 (0x06)
07 (0x07)
08 (0x08)
09 (0x09)
16 (0x10)
17 (0x11)
18 (0x12)
19 (0x13)
20 (0x14)
33 (0x21)
34 (0x22)
37 (0x25)
38 (0x26)
39 (0x27)
40 (0x28)
PIE
[01] INTERRUPT ENABLE AND EXTERNAL CONTROL
7
7
CIE
6
LFMM
LMVM
LCDM
LVDM
3DDM
6
LAGC
LS1M
LS0M
LSYM
MCM
LVM
LLM
CPD
WSE
DS1
PIE
7
Written on any write to [SSBase + 2],
Read from [SSBase + 2] when the indirect address is 0x00.
RW
RW
RW
RW
RW
TIE
5
5
CDE
RES
M20
CIE
RES
RES
RES
DS0
RES
6
RES
RES
RES
RES
RES
RES
RES
LAS [2:0]
VIE
4
External Control 0. The state of this bit is reflected on the XCTL0 pin. This pin is also muxed with
PCLKO. COF must be greater than 0x1011 for PCLKO to be disabled, see SS [32].
External Control 1. The state of this bit is reflected on the XCTL1 pin. XCTL1 may also be used for
Ring-In Interrupt. Open drain output, contains internal pull-up ~ 0.5 mA.
Timer Enable Bit.
SoundBlaster Interrupt Enable; This bit must be set to enable Current Count Timer.
0
1
Joystick Interrupt Enable;
0
1
4
TIE
RES
RES
DIT
PIW
5
(High Byte)
VER [15:8]
DIE
CNP
3
RES
VIE
PIR
3
FSMR [15:8]
MB0R [15:8]
MB1R [15:8]
4
VPSR [15.8]
VCSR [15:8]
S1SR [15:8]
S0SR [15:8]
PCC [15:8]
CBC [15:8]
CCC [15:8]
TBC [15:8]
TCC [15:8]
PBC [15:8]
PCR [15:8]
SoundBlaster Interrupt disabled
SoundBlaster Interrupt enabled
Joystick Interrupt disabled
Joystick Interrupt enabled
RES
RES
RES
RES
RES
RIE
Table VIII. Sound System Indirect Registers
DIE
PAA
2
2
3
LFMA [5:0]
LS1A [5:0]
LS0A [5:0]
3DD [3:0]
LVA [5:0]
LMVA [4:0]
LCDA [4:0]
LVDA [4:0]
LSYA [4:0]
MCA [4:0]
LLA [4:0]
ADR
PDA
RIE
JIE
1
2
1
LAG [3:0]
RES
PDP
I1T
JIE
SIE
1
0
0
–31–
PTB
RES
SIE
I0T
0
TE
7
7
RMVM
RFMM
RCDM
RVDM
RAGC
RS1M
RS0M
RSYM
VMU
RVM
RLM
POM
PIM
CPI
TE
3D
7
6
6
PD3D
VUP
RES
RES
RES
RES
PBI
5
6
COF [3:0]
5
RES
RES
RES
RES
RES
RES
RES
RAS [2:0]
GPSP
VDN
FMI
4
5
LBTD [7:0]
RES
4
RES
I1I
4
3
FMSR [7:0]
MB0R [7:0]
MB1R [7:0]
LBTD [7:0]
VPSR [7:0]
VCSR [7:0]
(Low Byte)
S1SR [7:0]
S0SR [7:0]
PBC [7:0]
PCC [7:0]
CBC [7:0]
CCC [7:0]
TBC [7:0]
TCC [7:0]
PCR [7:0]
VER [7:0]
3
RES
RES
RES
DM
I01
DEFAULT = [0xXX]
DEFAULT = [0x0102]
3
RFMA [5:0]
I2SF1 [1:0]
2
RS1A [5:0]
RS0A [5:0]
RVA [5:0]
2
RMVA [4:0]
RCDA [4:0]
RVDA [4:0]
RSYA [4:0]
POA [4:0]
RLA [4:0]
PIA [3:0]
BM [4:0]
2
RAG [3:0]
1
AD1816A
XC1
1
DFS [2:0]
XC1
RES
1
I2SF0 [1:0]
0
XC0
0
XC0
RES
0