AD1816 Analog Devices, AD1816 Datasheet - Page 33

• Manufacturer Part Number: AD1816
• Description: Single Chip Plug And Play Multimedia Audio Subsystem
• Manufacturer: Analog Devices

REV. A
RS0A [5:0]
RS0M
LS0A [5:0]
LS0M
PBC [15:0]
PCC [15:0]
CBC [15:0]
CCC [15:0]
LS0M
RS1M
LS1A [5:0]
LS1M
TBC [15:0]
[11] CAPTURE CURRENT COUNT
[08] PLAYBACK BASE COUNT
[09] PLAYBACK CURRENT COUNT
[10] CAPTURE BASE COUNT
[12] TIMER BASE COUNT
[07] I
7
7
7
7
7
7
2
S(0) ATTENUATION
RES
6
6
6
6
6
6
Right I
Left I
Left I
Right I
Right I
Left I
Left I
Playback Base Count. This register is for loading the Playback DMA Count. Writing a value to this register also
loads the same data into the Playback Current Count register. You must load this register when Playback Enable
(PEN) is deasserted. When PEN is asserted, the Playback Current Count decrements once for every four bytes
transferred via a DMA cycle. The next transfer, after zero is reached in the Playback Current Count, will generate
an interrupt and reload the Playback Current Count with the value in the Playback Base Count. The Playback Base
Count should always be programmed to Number Bytes divided by four, minus one ((Number Bytes/4) –1). The
circular software DMA buffer must be divisible by four to ensure proper operation.
Playback Current Count register. Contains the current Playback DMA Count. Reads and Writes must be done
when PEN is deasserted.
Capture Base Count. This register is for loading the Capture DMA Count. Writing a value to this register also
loads the same data into the Capture Current Count register. Loading must be done when Capture Enable (CEN)
is deasserted. When CEN is asserted, the Capture Current Count decrements once for every four bytes transferred
via a DMA cycle. The next transfer, after zero is reached in the Capture Current Count, will generate an interrupt
and reload the Capture Current Count with the value in the Capture Base Count. The Capture Base Count should
always be programmed to Number Bytes divided by four, minus one ((Number Bytes/4) –1). The circular software
DMA buffer must be divisible by four to ensure proper operation.
Capture Current Count register. Contains the current Capture DMA Count. Reading and Writing must be done
when CEN is deasserted.
Timer Base Count. Writing a value to this register loads data into the Timer Current Count register. Loading must
be done when Timer Enable (TE) is deasserted. When TE is asserted, the Timer Current Count register decre-
ments once for every specified time period. The time period (10 s or 100 ms) is programmed via the PTB bit in
SS [44]. When TE is asserted, the Timer Current Count decrements once every time period. The next count, after zero
is reached in the Timer Current Count register, will generate an interrupt and reload the Timer Current Count register
with the value in the Timer Base Count register.
5
5
5
5
5
5
2
2
2
2
S(1) Attenuation register. The LSB represents –1.5 dB, 000000 = 0 dB and the range is 0 dB to –94.5 dB.
S(1) Mute. 0 = Unmuted, 1 = Muted.
S(0) Attenuation register. The LSB represents –1.5 dB, 000000 = 0 dB and the range is 0 dB to –94.5 dB.
S(0) Mute. 0 = Unmuted, 1 = Muted.
2
2
2
S(1) Mute. 0 = Unmuted, 1 = Muted.
S(0) Attenuation register. The LSB represents –1.5 dB, 000000 = 0 dB and the range is 0 dB to –94.5 dB.
S(0) Mute. 0 = Unmuted, 1 = Muted.
CCC [15:8]
PBC [15:8]
PCC [15:8]
CBC [15:8]
TBC [15:8]
4
4
4
4
4
4
LS0A [5:0]
3
3
3
3
3
3
2
2
2
2
2
2
1
1
1
1
1
1
0
0
0
0
0
0
–33–
RS0M
7
7
7
7
7
7
RES
6
6
6
6
6
6
5
5
5
5
5
5
CCC [7:0]
PCC [7:0]
CBC [7:0]
TBC [7:0]
PBC [7:0]
4
4
4
4
4
4
3
3
3
3
3
3
RS0A [5:0]
DEFAULT = [0x0000]
DEFAULT = [0x0000]
DEFAULT = [0x8080]
DEFAULT = [0x0000]
DEFAULT = [0x0000]
DEFAULT = [0x0000]
2
2
2
2
2
2
AD1816A
1
1
1
1
1
1
0
0
0
0
0
0