AD1816 Analog Devices, AD1816 Datasheet - Page 36

• Manufacturer Part Number: AD1816
• Description: Single Chip Plug And Play Multimedia Audio Subsystem
• Manufacturer: Analog Devices

AD1816A
DFS [2:0]
I0I
I1I
FMI
PBI
CPI
I0T
I1T
ADR
DIT
DS0
DS1
FMSR [15:0] F Music Sample Rate register. The sample rate can be programmed from 4 kHz to 27.6 kHz in 1 hertz increments.
S1SR [15:0]
S0SR [15:0]
PCR [15:0]
3DDM
POA [4:0]
DS1
[35] I
[36] I
[33] DSP CONFIGURATION
[34] FM SAMPLE RATE
[37] RESERVED
[38] PROGRAMMABLE CLOCK RATE
[39] 3D Phat Stereo Control and PHONE_OUT Attenuation
7
7
7
7
7
7
7
2
2
S(1) SAMPLE RATE
S(0) SAMPLE RATE
DS0
6
6
6
6
6
6
6
RES
DSP Frame Sync Source. Sets the DSP Port Frame Sync according to the following source.
000—Maximum Frame Rate
001—I
010—I
011—Music Synthesizer Sample Rate
100—Sound System Playback Sample Rate
101—Sound System Capture Sample Rate
111—Reserved
I
I
FM Music Synthesizer Data Intercept. 0 = Disable, 1 = Intercept FM Music Data Enabled.
Playback Data Intercept. 0 = Disable, 1 = Intercept Playback Data Enabled.
Capture Data Intercept. 0 = Disable, 1 = Intercept Capture Data Enabled.
I
I
Audio Resync. Writing “1” causes all FIFOs in the DSP port to be re-initialized.
DSP Interrupt. A write to this bit causes an ISA interrupt if DIE is asserted.
DSP Mailbox 0 Status. 0 = last access indicates read, 1 = last access indicates write.
DSP Mailbox 1 Status. 0 = last access indicates read, 1 = last access indicates write.
I
Programming this register has no effect unless I
I
Programing this register has no effect unless I
2
2
2
2
2
2
S(0) Data Intercept. 0 = Disable, 1 = Intercept I
S(1) Data Intercept. 0 = Disable, 1 = Intercept I
S(0) Takeover Data. 0 = Disable, 1 = Enabled.
S(1) Takeover Data. 0 = Disable, 1 = Enabled.
S(1) Sample Rate register. The sample rate can be programmed from 4 kHz to 55.2 kHz in 1 hertz increments.
S(0) Sample Rate register. The sample rate can be programmed from 4 kHz to 55.2 kHz in 1 hertz increments.
Programmable Clock Rate register. The clock rate can be programmed from 25 kHz to 50 kHz in 1 hertz
increments. This register is only valid when the COF bits in SS [32] are set for the multiplier factor. PCLKO =
256
PHONE-OUT Attenuation. The LSB represents –1.5 dB, 0000 = 0 dB and the range is 0 dB to –46.5 dB.
DIT
RES
5
5
5
5
5
5
5
FMSR [15:8]
S1SR [15:8]
S0SR [15:8]
2
2
PCR [15:8]
S(0) Sample Rate
S(1) Sample Rate
PCR/2
4
4
4
4
4
4
4
RES
COF
. See SS [32] for determining the value of COF.
3DD [3:0]
3
3
3
3
3
3
3
ADR
2
2
2
2
2
2
2
I1T
1
1
1
1
1
1
1
RES
I0T
0
0
0
0
0
0
0
2
SF0 [1:0] is enabled.
–36–
2
SF1 [1:0] is enabled.
2
2
POM
CPI
S(0) Data Enabled.
S(1) Data Enabled.
7
7
7
7
7
7
7
PBI
6
6
6
6
6
6
6
RES
FMI
5
5
5
5
5
5
5
FMSR [7:0]
RES
I1I
S0SR [7:0]
S1SR [7:0]
PCR [7:0]
4
4
4
4
4
4
4
I0I
3
3
3
3
3
3
3
DEFAULT = [0xAC44]
DEFAULT = [0xAC44]
DEFAULT = [0xAC44]
DEFAULT = [0x5622]
POA [4:0]
DEFAULT = [0x0000]
DEFAULT = [0x0000]
DEFAULT = [0x8000]
2
2
2
2
2
2
2
DFS [2:0]
1
1
1
1
1
1
1
REV. A
0
0
0
0
0
0
0