AD1985 Analog Devices, AD1985 Datasheet - Page 16

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AD1985

Manufacturer Part Number
AD1985
Description
AC'97 2.3 Soundmax Codec W/jack Sensing
Manufacturer
Analog Devices
Datasheet

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AD1985
Headphone Volume Register (Index 0x04)
Reg Num
0x04
*For AC ’97 compatibility, Bit D7 (HPRM) is available only by setting the MSPLT bit in Register 0x76. The MSPLT bit enables separate mute bits for the left and right
channels.
This register controls the headphone volume controls for both
stereo channels and mute bit. Each volume subregister contains
five bits, generating 32 volume levels with increments of 1.5 dB
each. Because AC ’97 defines 6-bit volume registers, to maintain
compatibility, whenever the D5 or D13 bit is set to 1, its
respective lower five volume bits are automatically set to 1 by the
codec logic. On readback, all lower five bits will read 1s
whenever these bits are set to 1. See Volume Settings for Master
and Headphone table, above.
RHV[5:0]
HPRM
LHV[5:0]
HPM
Name
Headphones Volume
Right Headphone Volume Control. The least significant bit represents 1.5 dB. This register controls the output
from 0 dB to a maximum attenuation of 46.5 dB.
Right Channel Mute. Once enabled by the MSPLT bit in Register 0x76, this bit mutes the right channel separately
from the HPM bit. Otherwise this bit will always read 0 and will have no effect when set to 1.
Left Headphone Volume Control. The least significant bit represents 1.5 dB. This register controls the output
from 0 dB to a maximum attenuation of 46.5 dB.
Headphones Volume Mute. When this bit is set to 1, both the left and right channels are muted, unless the
MSPLT bit in Register 0x76 is set to 1, in which case this mute bit will only affect the left channel.
D15 D14 D13 D12 D11 D10 D9 D8 D7
HPM
X
X
LHV
4
Rev. 0 | Page 16 of 48
LHV
3
LHV
2
LHV
Note that depending on the state of the AC97NC bit in Register
0x76, this register has the following additional functionality:
For AC97NC = 0, the register has no control over the
SURR_OUT/HP_OUT outputs (see Register 0x38).
For AC97NC = 1, the register controls the
SURR_OUT/HP_OUT output attenuators.
1
LHV
0
HPRM* X
D6 D5 D4
X RHV
4
D3
RHV
3
D2
RHV
2
D1
RHV
1
D0
RHV
0
Default
0x8000

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