KSZ9021GN TR Micrel Inc, KSZ9021GN TR Datasheet - Page 21

• Manufacturer Part Number: KSZ9021GN TR
• Description: Specifications: Number of Drivers/Receivers: 8/8 ; Type: Transceiver ; Voltage - Supply: 3.135 V ~ 3.465 V ; Package / Case: 64-VFQFN Exposed Pad ; Packaging: Tape & Reel (TR) ; Protocol: Gigabit Ethernet ; Lead Free Status: Lead Free ; RoHS Stat
• Manufacturer: Micrel Inc

Micrel, Inc.
GMII Interface
The Gigabit Media Independent Interface (GMII) is compliant to the IEEE 802.3 Specification. It provides a common
interface between GMII PHYs and MACs, and has the following key characteristics:
In GMII operation, the GMII pins function as follow:
The KSZ9021GN combines GMII mode with MII mode to form GMII/MII mode to support data transfer at 10/100/1000
Mbps speed. After power-up or reset, the KSZ9021GN is configured to GMII/MII mode if the MODE[3:0] strap-in pins
are set to 0001. See Strapping Options section.
The KSZ9021GN has the option to output a low jitter 125MHz reference clock on CLK125_NDO (pin 55). This clock
provides a lower cost reference clock alternative for GMII/MII MACs that require a 125MHz crystal or oscillator. The
125MHz clock output is enabled after power-up or reset if the CLK125_EN strap-in pin is pulled high.
The KSZ9021GN provides a dedicated transmit clock input pin for GMII mode, defined as follow:
September 2010
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Pin count is 24 pins (11 pins for data transmission, 11 pins for data reception, and 2 pins for carrier and collision
indication).
1000Mbps is supported at both half and full duplex.
Data transmission and reception are independent and belong to separate signal groups.
Transmit data and receive data are each 8-bit wide, a byte.
The MAC sources the transmit reference clock, GTX_CLK, at 125MHz for 1000Mbps.
The PHY recovers and sources the receive reference clock, RX_CLK, at 125MHz for 1000Mbps.
TX_EN, TXD[7:0] and TX_ER are sampled by the KSZ9021GN on the rising edge of GTX_CLK.
RX_DV, RXD[7:0], and RX_ER are sampled by the MAC on the rising edge of RX_CLK.
CRS and COL are driven by the KSZ9021GN and are not required to transition synchronously with respect to
either GTX_CLK or RX_CLK.
GTX_CLK (input, pin 32):
Auto-Negotiation Interval Timers
Transmit Burst interval
Transmit Pulse interval
FLP detect minimum time
FLP detect maximum time
Receive minimum Burst interval
Receive maximum Burst interval
Data detect minimum interval
Data detect maximum interval
NLP test minimum interval
NLP test maximum interval
Link Loss time
Break Link time
Parallel Detection wait time
Link Enable wait time
Sourced by MAC in GMII mode for 1000Mbps speed
Table 2. Auto-Negotiation Timers
Time Duration
16 ms
68 us
17.2 us
185 us
6.8 ms
112 ms
35.4 us
95 us
4.5 ms
30 ms
52 ms
1480 ms
830 ms
1000 ms
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M9999-091010-1.1
KSZ9021GN