KSZ9021GN TR Micrel Inc, KSZ9021GN TR Datasheet - Page 6

• Manufacturer Part Number: KSZ9021GN TR
• Description: Specifications: Number of Drivers/Receivers: 8/8 ; Type: Transceiver ; Voltage - Supply: 3.135 V ~ 3.465 V ; Package / Case: 64-VFQFN Exposed Pad ; Packaging: Tape & Reel (TR) ; Protocol: Gigabit Ethernet ; Lead Free Status: Lead Free ; RoHS Stat
• Manufacturer: Micrel Inc

Micrel, Inc.
KSZ9021GN
List of Figures
Figure 1. KSZ9021GN Block Diagram ..............................................................................................................................15
Figure 2. KSZ9021GN 1000Base-T Block Diagram – Single Channel.............................................................................17
Figure 3. Auto-Negotiation Flow Chart..............................................................................................................................20
Figure 4. KSZ9021GN GMII Interface...............................................................................................................................22
Figure 5. KSZ9021GN MII Interface .................................................................................................................................24
Figure 6. GMII Transmit Timing – Data Input to PHY .......................................................................................................44
Figure 7. GMII Receive Timing – Data Input to MAC .......................................................................................................45
Figure 8. MII Transmit Timing – Data Input to PHY ..........................................................................................................46
Figure 9. MII Receive Timing – Data Input to MAC ..........................................................................................................47
Figure 10. Auto-Negotiation Fast Link Pulse (FLP) Timing ..............................................................................................48
Figure 11. MDC/MDIO Timing...........................................................................................................................................49
Figure 12. Reset Timing....................................................................................................................................................50
Figure 13. Recommended Reset Circuit...........................................................................................................................50
Figure 14. Recommended Reset Circuit for Interfacing with CPU/FPGA Reset Output. .................................................51
Figure 15. Reference Circuits for LED Strapping Pins......................................................................................................51
Figure 16. 25MHz Crystal / Oscillator Reference Clock Connection ................................................................................52
September 2010
6
M9999-091010-1.1