KSZ9021GN TR Micrel Inc, KSZ9021GN TR Datasheet - Page 25

• Manufacturer Part Number: KSZ9021GN TR
• Description: Specifications: Number of Drivers/Receivers: 8/8 ; Type: Transceiver ; Voltage - Supply: 3.135 V ~ 3.465 V ; Package / Case: 64-VFQFN Exposed Pad ; Packaging: Tape & Reel (TR) ; Protocol: Gigabit Ethernet ; Lead Free Status: Lead Free ; RoHS Stat
• Manufacturer: Micrel Inc

Micrel, Inc.
MII Management (MIIM) Interface
The KSZ9021GN supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input/
Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the KSZ9021GN.
An external device with MIIM capability is used to read the PHY status and/or configure the PHY settings. Further detail
on the MIIM interface can be found in Clause 22.2.4.5 of the IEEE 802.3 Specification.
The MIIM interface consists of the following:
The following table shows the MII Management frame format for the KSZ9021GN.
Interrupt (INT_N)
INT_N (pin 53) is an optional interrupt signal that is used to inform the external controller that there has been a status
update in the KSZ9021GN PHY register. Bits [15:8] of register 27 (1Bh) are the interrupt control bits to enable and
disable the conditions for asserting the INT_N signal. Bits [7:0] of register 27 (1Bh) are the interrupt status bits to
indicate which interrupt conditions have occurred. The interrupt status bits are cleared after reading register 27 (1Bh).
Bit 14 of register 31 (1Fh) sets the interrupt level to active high or active low. The default is active low.
The MII management bus option gives the MAC processor complete access to the KSZ9021GN control and status
registers. Additionally, an interrupt pin eliminates the need for the processor to poll the PHY for status change.
LED Mode
The KSZ9021GN provides two programmable LED output pins, LED2 and LED1, which are configurable to support two
LED modes. The LED mode is configured by the LED_MODE strap-in (pin 55). It is latched at power-up / reset and is
defined as follows:
September 2010
•
•
•
•
•
Read
Write
A physical connection that incorporates the clock line (MDC) and the data line (MDIO).
A specific protocol that operates across the aforementioned physical connection that allows an external
controller to communicate with one or more KSZ9021GN device. Each KSZ9021GN device is assigned a PHY
address between 1 and 7 by the PHYAD[2:0] strapping pins.
A 32 register address space to access the KSZ9021GN IEEE Defined Registers, Vendor Specific Registers and
Extended Registers. See Register Map section.
Pull-up:
Pull-down: Tri-color Dual LED Mode
Preamble
32 1’s
32 1’s
Single LED Mode
Start of
Frame
01
01
Table 5. MII Management Frame Format – for KSZ9021GN
Read/Write
OP Code
10
01
PHY
Address
Bits [4:0]
00AAA
00AAA
25
REG
Address
Bits [4:0]
RRRRR
RRRRR
TA
Z0
10
Data
Bits [15:0]
DDDDDDDD_DDDDDDDD
DDDDDDDD_DDDDDDDD
M9999-091010-1.1
KSZ9021GN
Idle
Z
Z