AD8305 Analog Devices, AD8305 Datasheet - Page 9

• Manufacturer Part Number: AD8305
• Description: 100 Db-range (10nA-1mA) Logarithmic Converter
• Manufacturer: Analog Devices

GENERAL STRUCTURE
The AD8305 addresses a wide variety of interfacing conditions
to meet the needs of fiber optic supervisory systems, and will
also be useful in many nonoptical applications. These notes
explain the structure of this unique style of translinear log amp.
Figure 1 is a simplified schematic showing the key elements.
The photodiode current I
voltage at this node is essentially equal to those on the two
adjacent guard pins, VSUM and IREF, due to the low offset
voltage of the JFET op amp. Transistor Q1 converts the input
current I
Equation 1. A finite positive value of V
the collector of Q1 for the usual case of a single-supply voltage.
This is internally set to 0.5 V, that is, one fifth of the reference
voltage of 2.5 V appearing on Pin VREF. The resistance at the
VSUM pin is nominally 16 kW; this voltage is not intended as
a general bias source.
The AD8305 also supports the use of an optional negative supply
voltage, V
VSUM may be connected to ground; thus INPT and IREF
assume this potential. This allows operation as a voltage-input
logarithmic converter by the inclusion of a series resistor at either
or both inputs. Note that the resistor setting I
adjusted to maintain the intercept value. It should also be noted
that the collector-emitter voltages of Q1 and Q2 are now the full
V
input currents.
The input dependent V
V
ated externally, to a recommended value of 10 mA. However,
other values over a several-decade range can be used with a
slight degradation in law conformance (TPC 1).
Theory
The base-emitter voltage of a BJT (bipolar junction transistor)
can be expressed by Equation 1, which immediately shows its
basic logarithmic nature:
where I
only 10
absolute temperature (PTAT) and is 25.85 mV at 300 K. The
current, I
ger temperature dependence, varying by a factor of roughly a
REV. A
INPUT CURRENT
PHOTODIODE
N
BE2
, and effects due to self-heating will cause errors at large
I
INPT
PD
V
of a second transistor, Q2, operating at I
BE
Q1
C
–17
0.5V
PD
VNEG (NORMALLY GROUNDED)
is its collector current, I
S
N
=
A, and kT/q is the thermal voltage, proportional to
, is never precisely defined and exhibits an even stron-
, at Pin VNEG. When V
kT q
to a corresponding logarithmic voltage, as shown in
GENERATOR
VSUM
80k
2.5V
0.5V
/
Figure 1. Simplified Schematic
BIAS
In
(
20k
I I
C
V
/
BE1
VREF
S
BE1
COMM
)
PD
0.5V
of Q1 is compared with the reference
IREF
is received at Pin INPT. The
Q2
I
S
REF
is a scaling current, typically
N
is –0.5 V or more negative,
SUM
V
V
V
BE1
BE2
BE2
VRDZ
is needed to bias
TEMPERATURE
COMPENSATION
(SUBTRACT AND
DIVIDE BY T
REF
REF
14.2k
6.69k
. This is gener-
will need to be
44 A/dec
451
COMM
K
VLOG
(1)
–9–
billion between –35∞C and +85∞C. Thus, to make use of the
BJT as an accurate logarithmic element, both of these tempera-
ture dependencies must be eliminated.
The difference between the base-emitter voltages of a matched pair
of BJTs, one operating at the photodiode current I
operating at a reference current I
The uncertain and temperature dependent saturation current I
which appears in Equation 1, has thus been eliminated. To
eliminate the temperature variation of kT/q, this difference voltage
is processed by what is essentially an analog divider. Effectively, it
puts a variable under Equation 2. The output of this process,
which also involves a conversion from voltage-mode to current-
mode, is an intermediate, temperature-corrected current:
where I
determines the slope of the function (the change in current per
decade). For the AD8305, I
independent slope of 44 mA/decade, for all values of I
This current is subsequently converted back to a voltage-mode
output, V
It is apparent that this output should be zero for I
would need to swing negative for smaller values of input current.
To avoid this, I
value of I
ence current as 1 nA. Accordingly, an offset voltage is added to
V
connected to VREF. This has the effect of moving the intercept
to the left by four decades, from 10 mA to 1 nA:
where I
disable this offset, Pin VRDZ should be grounded, then the
intercept I
a negative V
to accommodate this situation (discussed later).
The voltage V
resistance of 4.55 kW, formed by the parallel combination of a
6.69 kW resistor to ground and the 14.2 kW resistor to the VRDZ
pin. When the VLOG pin is unloaded and the intercept reposi-
tioning is disabled by grounding VRDZ, the output current I
generates a voltage at the VLOG pin of:
where V
loading on VLOG will lower this slope and also result in an
overall scaling uncertainty due to the variability of the on-chip
resistors. Consequently, this practice is not recommended.
V
V
and IREF may now be positioned at ground level by simply
grounding VSUM.
LOG
LOG
N
) are used. When V
V
V
to shift it upward by 0.8 V when Pin VRDZ is directly
may also swing below ground when dual supplies (V
I
I
BE1
LOG
LOG
LOG
Y
INTC
Y
is an accurate, temperature-stable scaling current that
PD
LOG
= 200 mV/decade, or 10 mV/dB. Note that any resistive
–
INTC
=
=
=
V
=
=
. However, it is impractical to use such a small refer-
is the operational value of the intercept current. To
LOG
V
BE2
I
44
I
, scaled 200 mV/decade.
I
LOG
Y
Y
LOG
Y
is simply I
REF
, a negative supply of sufficient value is required
log
log
m
log
=
=
=
A
is generated by applying I
¥
kT q
10
would need to be as small as the smallest
10
10
59 5
In 10
¥
4 55
(
(
(
.
4 55
/
( )
I
I
I
.
N
PD
PD
.
PD
In
= –0.5 V or larger, the input pins INPT
mV
REF
k
/
/
/
I
I
I
(
kT q
k
REF
INTC
W
I I
REF
Y
C
. Since values of I
W
log
is 44 mA, resulting in a temperature-
/
/ log
)
)
¥
S
REF
)
10
)
log
–
(
, can be written as:
10
I
kT q
PD
10
(
I
(
/
PD
I
/
I
REF
PD
/
In
I
/
REF
I
(
)
LOG
REF
I
(
T
REF
PD
)
PD
)
=
AD8305
to an internal
PD
/
< I
I
300
and the second
S
= I
)
INTC
PD
K
REF
and I
result in
)
, and
P
LOG
and
REF
(2)
(3)
(4)
(5)
S
,
.