MTSF3N03HD ON Semiconductor, MTSF3N03HD Datasheet - Page 7

• Manufacturer Part Number: MTSF3N03HD
• Description: Hdtmos Power MOSFETs, Micro8, Single N-channel, VDSS 30
• Manufacturer: ON Semiconductor

14) defines the maximum simultaneous drain–to–source
voltage and drain current that a transistor can handle safely
when it is forward biased. Curves are based upon maximum
peak junction temperature and a case temperature (T C ) of
25 C. Peak repetitive pulsed power limits are determined by
using the thermal response data in conjunction with the
procedures discussed in AN569, “Transient Thermal
Resistance – General Data and Its Use.”
traverse any load line provided neither rated peak current
(I DM ) nor rated voltage (V DSS ) is exceeded, and that the
transition time (t r , t f ) does not exceed 10 s. In addition the
total power averaged over a complete switching cycle must
not exceed (T J(MAX) – T C )/(R JC ).
in switching circuits with unclamped inductive loads. For
The Forward Biased Safe Operating Area curve (Figure
Switching between the off–state and the on–state may
A power MOSFET designated E–FET can be safely used
Figure 14. Maximum Rated Forward Biased
Safe Operating Area
Figure 13. Reverse Recovery Time (t rr )
SAFE OPERATING AREA
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MTSF3N03HD
7
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and must be adjusted for operating
conditions differing from those specified. Although industry
practice is to rate in terms of energy, avalanche energy
capability is not a constant. The energy rating decreases
non–linearly with an increase of peak current in avalanche
and peak junction temperature.
drain–to–source avalanche at currents up to rated pulsed
current (I DM ), the energy rating is specified at rated
continuous current (I D ), in accordance with industry
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 15). Maximum
energy at currents below rated continuous I D can safely be
assumed to equal the values indicated.
Although many E–FETs can withstand the stress of
Figure 15. Maximum Avalanche Energy versus
Starting Junction Temperature