MT93L04 Zarlink Semiconductor, MT93L04 Datasheet - Page 12

• Manufacturer Part Number: MT93L04
• Description: 128-channel Voice Echo Canceller
• Manufacturer: Zarlink Semiconductor

Pin Description (continued)
Tsig(11)_d2
Tsig(12)_d2
Tsig(13)_d2
Tsig(15)_d2
MCLK_d2
Fsel_d2
Step_d2
PLLVSS1_d2
PLLVDD_d2
PLLVSS2_d2
AT1_d2
DEVICE 3
TMS_d3
Tsig(14)_d2
Tm1_d2
Tm2_d2
Sg1_d2
DT1_d2
Halt_d2
Signal Name
NC
NC
NC
NC
NC
ICO
ICO
ICO
NC
Signal
Signal
ICO
ICO
Power
Power
Power
NC
Signal
Signal Type
BGA Ball #
W13
W1
W2
R1
R2
U1
R3
R4
V1
U2
Y1
U3
V3
Zarlink Semiconductor Inc.
P3
T1
T2
T3
V2
MT93L04
12
No connection. The pin must be left open for
normal operation.
No connection. The pin must be left open for
normal operation.
No connection. The pin must be left open for
normal operation.
No connection. The pin must be left open for
normal operation.
No connection. The pin must be left open for
normal operation.
Internal Connection. Connected to VSS for
normal operation
Internal Connection. Connected to VSS for
normal operation
Internal Connection. Connected to VSS for
normal operation
No connection. The pin must be left open for
normal operation.
Master Clock (Input). Nominal 10 MHz or
20 MHz Master Clock input. May be connected to
an asynchronous (relative to frame signal) clock
source.
Frequency select (Input). This input selects the
Master Clock frequency operation. When Fsel pin
is low, nominal 19.2 MHz Master Clock input must
be applied. When Fsel pin is high, nominal
9.6 MHz Master Clock input must be applied.
Internal Connection. Connected to VSS for
normal operation
Internal Connection. Connected to VSS for
normal operation
PLL Ground. Must be connected to VSS
PLL Power Supply. Must be connected to VDD2
PLL Ground. Must be connected to VSS
No connection. The pin must be left open for
normal operation.
Test Mode Select (3.3 V Input). JTAG signal that
controls the state transitions of the TAP controller.
This pin is pulled high by an internal pull-up when
not driven.
Signal Description
Data Sheet