MT93L04 Zarlink Semiconductor, MT93L04 Datasheet - Page 43

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MT93L04

Manufacturer Part Number
MT93L04
Description
128-channel Voice Echo Canceller
Manufacturer
Zarlink Semiconductor
Datasheet

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Echo Canceller A, Error Peak Detect Register 1 (EP)
Echo Canceller B, Error Peak Detect Register 1 (EP)
Echo Canceller A, Double-Talk Detection Threshold Register 2 Read/Write Address:
Echo Canceller B, Double-Talk Detection Threshold Register 2 Read/Write Address:
This register allows the user to program the level of Double-Talk Detection Threshold (DTDT). The 16 bit 2’s
complement linear value defaults to 4800h= 0.5625 or -5 dB. The maximum value is 7FFFh = 0.9999 or 0
dB. The high byte is in Register 2 and the low byte is in Register 1.
Echo Canceller A, Error Peak Detect Register 2 (EP)
Echo Canceller B, Error Peak Detect Register 2 (EP)
These peak detector registers allow the user to monitor the error signal peak level. The information is in
16-bit 2’s complement linear coded format presented in two 8 bit registers for each echo canceller. The
high byte is in Register 2 and the low byte is in Register 1.
Echo Canceller A, Double-Talk Detection Threshold Register 1 Read/Write Address:
Echo Canceller B, Double-Talk Detection Threshold Register 1 Read/Write Address:
EP15
EP7
DTDT15 DTDT14 DTDT13
DTDT7
7
7
7
7
EP14
EP6
DTDT6
6
6
6
6
EP13
EP5
DTDT5
5
5
5
5
EP12
EP4
4
4
DTDT4
DTDT12
4
4
EP11
EP3
3
3
DTDT11
DTDT3
3
3
Zarlink Semiconductor Inc.
EP10
EP2
2
2
MT93L04
DTDT2
DTDT10 DTDT9
2
2
43
EP9
EP1
1
1
DTDT1
1
1
EP8
EP0
0
0
DTDT0
DTDT8
0
Read Address:
Read Address:
Read Address:
Read Address:
0
(DTDT)
(DTDT)
11h
31h
10h
30h
+ Base Address
+ Base Address
+ Base Address
+ Base Address
Power Reset Value
Power Reset Value
15h
35h
14h
34h
Power Reset Value
Power Reset Value
+ Base Address
+ Base Address
+ Base Address
+ Base Address
48h
N/A
00h
N/A
Data Sheet

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