MT93L04 Zarlink Semiconductor, MT93L04 Datasheet - Page 25

• Manufacturer Part Number: MT93L04
• Description: 128-channel Voice Echo Canceller
• Manufacturer: Zarlink Semiconductor

The NLPTHR register is 16 bits wide. The register value in hexadecimal can be calculated with the following
equation:
The comfort noise injector can be disabled by setting the INJDis bit to “1” in Control Register A1/B1. It should be
noted that the NLPTHR is valid and the comfort noise injection is active only when the NLP is enabled.
If the comfort noise injector is unable to correctly match the level of the background noise (because of peculiar
spectral characteristics, for example), the injected level can be fine-tuned using the Noise Scaling register. A
neutral value of 80(hex) will prevent any scaling. Values less than 80(hex) will reduce the noise level, values greater
than 80(hex) will increase the noise level. The scaling is done linearly.
Example: To decrease the comfort noise level by 3 dB, the register value would be 10 ^ (-3 / 20) • 128 = 0.71 • 128
= 91(dec) = 5B(hex)
The default factory setting for the Noise Scaling register should be adequate for most operating environments. It is
unlikely that it will need to be changed. It has also been set to a value which will ensure G.168 compliance.
Disable Tone Detector
G.165 recommendation defines the disable tone as having the following characteristics: 2100 Hz (±21 Hz) sine
wave, a power level between -6 to -31 dBm0, and a phase reversal of 180 degrees (± 25 degrees) every 450 ms (±
25 ms). If the disable tone is present for a minimum of one second with at least one phase reversal, the Tone
Detector will trigger.
G.164 recommendation defines the disable tone as a 2100 Hz (±21 Hz) sine wave with a power level between 0 to
-31 dBm0. If the disable tone is present for a minimum of 400 milliseconds, with or without phase reversal, the Tone
Detector will trigger.
The MT93L00 has two Tone Detectors per channels (for a total of 64) in order to monitor the occurrence of a valid
disable tone on both Rin and Sin. Upon detection of a disable tone, TD bit of the Status Register will indicate logic
high and an interrupt is generated (i.e., IRQ pin low). Refer to Figure 5 and to the Interrupts section.
Once a Tone Detector has been triggered, there is no longer a need for a valid disable tone (G.164 or G.165) to
maintain Tone Detector status (i.e., TD bit high). The Tone Detector status will only release (i.e., TD bit low) if the
signals Rin and Sin fall below -30 dBm0, in the frequency range of 390 Hz to 700 Hz, and below -34 dBm0, in the
Rin
Sin
Rin
Sin
NLPTHR(hex) = hex(NLPTHR(dec) * 32768)
Figure 5 - Disable Tone Detection
where 0 < NLPTHR
Tone Detector
Tone Detector
Tone Detector
Tone Detector
Zarlink Semiconductor Inc.
Echo Canceller A
Echo Canceller B
MT93L04
25
(dec)
< 1
Status reg
Status reg
TD
TD bit
ECA
ECB
bit
Data Sheet