MT8926 Zarlink Semiconductor, MT8926 Datasheet - Page 16

• Manufacturer Part Number: MT8926
• Description: T1 Performance Monitoring Adjunct Circuit (PMAC)
• Manufacturer: Zarlink Semiconductor

SEMICMF.019
Data Sheet
The BPV and CRC counters, as well as the BSI and CSI bits, are cleared by a high-to-low transition of bit 4, BPV
Counter Reset (BPVR), and bit 5, CRC Counter Reset (CRCR), of the PMAC Control Word channel 11 CSTi1,
Table 14 on page 16.
1.12
An AIS or Blue alarm is an all ones signal that can be transmitted from the network side to the terminal equipment
side of an interface or from the terminal equipment side to the network side of an interface. In the first case, it
indicates that the T1 signal from the network may be lost, and the timing that the terminal equipment derives from
the received AIS may not be from the network. In the second case, it indicates that data from the terminal equipment
side of an interface has been lost and AIS is being transmitted in its place.
The MT8926 will detect an AIS alarm and indicate its presence by making the AIS bit of Master Status Word 2
(Table 11 on page 14, CSTo channel 31 bit 0) high. This state occurs when the MT8976/77 has lost synchronization
and less than three zeros are detected in any 250 microsecond interval. The AIS bit will go low when either of these
conditions is no longer true.
1.13
The MT8926 will support the transfer of FDL bit-oriented messages in a format that is consistent with T1.403 and
T1.408. A BOM is transmitted by loading the message into the PMAC Transmit Bit-Oriented Message Register
(TxBOM), Table 13 on page 15, CSTi1 Channel 7. This data has the form 0XXXXXX0, where XXXXXX is the
content of the T1.403/408 message. When FDLEn (bit zero of the PMAC Control Word, Table 14 on page 16) is
made high, the BOM is transmitted on the FDL preceded by 11111111. The start of the bit-oriented message is not
synchronous with FDLEn going high. Therefore, to ensure a message is sent a minimum of n times, the message
must be transmitted for 32n + 32 ST-BUS frames.
Valid codewords that are received on the FDL are loaded into the Receive Bit-Oriented Message Register (RxBOM,
see Table 12 on page 15). A codeword is valid if it fits the 11111111 0XXXXXX0 form, however, only the
0XXXXXX0 portion of the message will appear in the RxBOM register. When a valid codeword has been received
7-0
Bit
7-0
Bit
Alarm Indication Signal (AIS)
MT8926 FDL Message Transfer
RxBOM
TxBOM
Name
Name
Table 12 - Receive Bit-Oriented Message Register (CSTo Channel 27)
Table 13 - Transmit Bit-Oriented Message Register (CSTi1 Channel 7)
Received Bit-Oriented Message. This register contains the eight least significant
bits of the ESF bit oriented message codeword. The contents of this register is valid
when a bit-oriented message codeword is received by the MT8926 in the facility
data link bit positions of consecutive extended superframes. A valid codeword will
have the form 111111110XXXXXX0. The most significant eight bits (FF sequence)
are received first. The register will contain the eight bits following the 11111111
sequence, which are 0XXXXXX0.
When a valid codeword is detected, bit zero of the PMAC Miscellaneous Status
Register is set.
Transmit Bit-Oriented Message. The contents of this register will be appended to an
FF flag to form a bit-oriented codeword, and clocked out on FDLo when bit zero in
the PMAC Control Word is set high. The MT8926 will continue to clock this message
out until bit 0 in the Control word is reset. The order of transmission is Bit 7 first.
Bits 7 and 0 should be zero for a code word to be valid.
Description
Description
MT8926
15